Intrinsity, Inc.

Kenneth D Amstutz

Stephen C Horne

The present invention comprises a number transformer that includes an encoder that converts binary numbers to N-NARY numbers. Within an N-NARY number, exactly one of the bits has a value of one and all of the remaining bits have a value of zero. According to some aspects, several N-NARY numbers are generated in response to a binary number. A set of encoding instance selectors defines a partitioning of the bits of the binary number and a range of bits within each partition. The encoder then converts each subset of bits of the binary number to a corresponding N-NARY number, such that exactly one of the bits of each N-NARY number has a value of one and all of the remaining bits of the N-NARY number have a value of zero, and such that the one of the bits of each N-NARY number having a value of one is within the range of bits defined by the corresponding encoding instance selector. The set of encoding instance selectors may define a test point within a circuit under test, and may be produced by an on-chip ROM.

Method and apparatus for transforming pseudorandom binary patterns into test stimulus patterns appropriate for circuits having 1 of N encoded inputs

The present invention is a method and apparatus that initializes N-NARY logic and dynamic logic to a special stress mode. The present invention has a logic circuit that includes a shared logic tree with one or more evaluate nodes, one or more precharge devices, and an evaluate device. Coupled to the evaluate nodes is a state generation control circuit that generates a state signal. A state generation circuit receives the state signal from the state generation control circuit and initializes the evaluate nodes to a functionally illegal state that initializes the logic circuit to the special stress mode. One embodiment of the present invention initializes the evaluate nodes to a low state. When the first logic circuit in a series of logic circuits is initialized to the functionally illegal state, the present invention will initialize the succeeding logic circuits in the series as each phase in the different clock domains evaluate, which initializes the succeeding logic circuits to the special stress mode.

Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state

The present invention comprises a number transformer that includes at least one updatable parameter, for example a ring counter, that produces an N-nary number. The N-nary number has several bits, exactly one of which has a value of one and the remaining of which have a value of zero. The number transformer also includes a masker, configured to perform a bitwise boolean AND upon the first updatable parameter and a binary number. The binary number is obtained from a linear finite state machine operating as a pseudorandom pattern generator. When several ring counters are included, multiplexers are added to select one of the ring counters. The multiplexers are controlled by a ROM, that iterates through the various test points in a circuit under test.

Method and apparatus for transforming pseudorandom binary test patterns into test stimulus patterns appropriate for circuits having 1 of N encoded inputs

The present invention comprises a method and apparatus for built-in self-test of logic circuitry for logic under test. The logic under test comprises a plurality of test points, each test point having a plurality of nodes. The test circuitry comprises a linear finite state machine. The linear finite state machine generates subsequent states that are non-sequential, pseudorandom binary numbers stochastically determined by a characteristic polynomial of the linear finite state machine. Moreover, the contents of the linear finite state machine are readable or writable via scan. The preferred implementation also comprises a test data bus coupled between the logic under test and the linear finite state machine. The test data bus is configured to convey data in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points.

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Austin, TX, United States of America

Kenneth D Amstutz