Qualcomm Incorporated

Kenneth Charles Barnett

Harish S Muthali

Susanta Sengupta

Tae Wook Kim

Kun Zhang

Gurkanwal Singh Sahota

Vladimir Aparin

Brett Christopher Walker

Kevin Glenn Gard

Namsoo Kim

Guy Klemens

Manas Behera

Charles James Persico

Paul E Peterzell

Yunfei Feng

Bo Yang

Gaurab Banerjee

Susanta Sangupta

An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals.

Amplifier with integrated filter

A built-in self test (BiST) system is described. The BiST system includes a circuit-under-test. The BiST system also includes one or more embedded sensors. Each of the embedded sensors includes one or more switches connected to one or more nodes within the circuit-under-test. The BiST system further includes a signal generator. The BiST system also includes a bus interface. The bus interface provides for external access of the BiST system.

Methods and apparatus for providing a built-in self test

A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.

Latch structure, frequency divider, and methods for operating same

Techniques for designing a highly differential single-ended-to-differential converter for use in, e.g., communications receivers. In an exemplary embodiment, an auxiliary current path including cascomp transistors is coupled to a main current path including input transistors and cascode transistors. The transistors are biased such that inter-modulation products generated by the auxiliary current path cancel out inter-modulation products generated by the main current path. In another exemplary embodiment, current source transistors for the main current path are adaptively biased depending on the level of the input signal received. In an exemplary embodiment, the techniques may be applied to designing a converter for interfacing a single-ended low-noise amplifier (LNA) output voltage with a differential mixer input in a communications receiver.

RF single-ended to differential converter

The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground.

Linear transconductor for RF communications

A differential Low Noise Amplifier (LNA) includes a first stage of resistive feedback amplifiers and second stage of complementary amplifiers, where the outputs of the first stage are coupled to the inputs of the second stage in a cross-coupled fashion. An inductive load, such as a transformer, combines signals output from the complementary amplifiers of the second stage. In one example, the LNA has an input impedance of less than 75 ohms, a noise factor of less than 2 dB, and a gain of more than 20 dB. Due to the low input impedance, the LNA is usable to amplify a signal received from a source having a similar low impedance without the use of an impedance matching network between the output of the source and the input of the LNA.

Noise-canceling for differential amplifiers requiring no external matching

A phase locked loop apparatus includes an oscillator, a variable capacitance device, a selectable capacitance device, and a capacitance controller that is configured to provide a control signal to the selectable capacitance device. The selectable capacitance device is connected to the oscillator and is responsive to the control signal such that the selectable capacitance device has a first capacitance at a first control signal value and a second capacitance at a second control signal value. The capacitance controller only selects either the first capacitance or the second capacitance by providing a control signal that has the first control signal value to select the first capacitance and having the second control signal value to select the second capacitance.

Phase locked loop apparatus with selectable capacitance device

This disclosure is directed to a frequency-selective low noise amplifier (LNA) with wide-band impedance and noise matching. The LNAS may include a closed loop circuit that supports wideband input matching. For example, the closed loop circuit may be configure to impedance match an input signal and provide a low noise figure. In addition, the LNA may include an open loop circuit that amplifies the input signal and provides a high output impedance. The open loop circuit may further include a selectivity filter that filters out frequencies outside a desired frequency band. The LNA may drive a tunable band-pass filter via the open loop circuit.

Frequency selective amplifier with wide-band impedance and noise matching

An amplifier, which has good linearity and noise performance, includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier.

Amplifier with active post-distortion linearization

A differential amplifier, which has good linearity and noise performance, includes a first side that includes first, second, third, and fourth transistors and an inductor. The first and second transistors are coupled as a first cascode pair, and the third and fourth transistors are coupled as a second cascode pair. The third transistor has its gate coupled to the source of the second transistor, and the fourth transistor has its drain coupled to the drain of the second transistor. The first transistor provides signal amplification. The second transistor provides load isolation and generates an intermediate signal for the third transistor. The third transistor generates distortion components used to cancel third order distortion component generated by the first transistor. The inductor provides source degeneration for the first transistor and improves distortion cancellation. The sizes of the second and third transistors are selected to reduce gain loss and achieve good linearity for the amplifier. The differential amplifier also may include a second side that functions similarly to the first side.

Differential amplifier with active post-distortion linearization

Techniques for generating a signal having a predetermined duty cycle. In an exemplary embodiment, a first counter is configured to count a first number of cycles of an oscillator signal, and a second counter is configured to count a second number of cycles of the oscillator signal, with the second number being greater than the first number. The output of the second counter is used to reset the first and second counters, while the outputs of the first and second counters further drive a toggle latch for generating the signal having predetermined duty cycle. Further aspects include techniques for accommodating odd and even values for the second number.

Predetermined duty cycle signal generator

A bandgap voltage reference circuit and methods for generating a bandgap reference voltage are disclosed. An operational amplifier receives first and second input voltages from a first and second current path, respectively. A buffer stage is coupled to an output of the operational amplifier and generates third and fourth voltages on the first and second path. A temperature dependent current is generated using the third and fourth voltages in combination with a first diode, second diode and a resistor. A third current path mirrors the temperature dependent current and a temperature independent voltage is generated for the bandgap reference voltage in the third current path using the temperature dependent current in combination with a second resistor and related diode.

Growing community of inventors

Austin, TX, United States of America

Kenneth Charles Barnett