International Business Machines Corporation

Kenneth Chang

Ananda H Kumar

George Czornyj

Heinz O Steimel

Mukta S Farooq

George T Chiu

Helmut M Gartner

Anthony J Hoeg, Jr

Marvin S Pittler

Marvin S Pitler

Anthony Hoeg, Jr

Linda H Lee

David C Cosman

A method of making a multilayer thin film structure on the surface of a dielectric substrate which includes the steps of:

Method of making a multilayer thin film structure

The present invention provides a packaging semiconductor structure and method for obtaining same. The structure is comprised of at least one level of dielectric and metallurgy layers. The at least one level is comprised of a wiring metallurgy plane and a 'through-via' plane of interconnecting metallurgy in association with both one and two layers of polymeric dielectric materials. The self-alignment method of fabrication of the level provides a streamlined technique wherein stringent masking and alignment requirements are relaxed, undue processing such as at least one polishing step is eliminated and a structure having adhesive integrity is fabricated.

Layer thin film wiring process featuring self-alignment of vias

Multi layer thin film wiring process featuring self-alignment of vias

A process for forming a layer of a metallurgy interconnection system on a substrate. The process involves forming a first electrically insulative layer of an organic polymerized resin material on the substrate, forming a second thin layer on the first layer which is resistant to dry etching conditions which are effective to etch the first layer, depositing a photoresist layer on the second layer, exposing the photoresist to form an inverse pattern of a desired metallurgy pattern and developing the photoresist, reactive ion etching the resultant exposed areas of the first and second layers, depositing a blanket continuous conductive metal layer over the hills and valleys of the pattern resulting from reactive ion etching, applying a planarizing photoresist layer, etching the photoresist to expose high spots of the metal layer, and etching the metal high spots to a depth sufficient to expose the surface of the second layer.

Planar metal interconnection system and process

A method for forming thin film interconnection patterns atop substrates, particularly semiconductor substrates. It features the use of the passivation layer itself, typically glass, as a stable masking material to etch the conductive lines. Conversely, the metal conductor is used as a stable mask in etching the glass to form via holes. The process provides a practical resist system which is compatible with reactive ion etching or other dry etching process.

Method of forming thin film interconnection systems

In integrated circuit fabrication, a method is provided for forming metallic connectors through a layer of electrically insulative material. The method comprises forming a layer of electrically insulative material on a substrate and then forming a mask of photoresist material having a plurality of openings through which said insulative layer is exposed on said insulative layer. Then, the exposed portions of said insulative layer are removed by etching to form openings through which the underlying substrate is exposed, after which a first metal layer is deposited over the masked substrate. This metal layer is thinner than the insulative layer so that the openings in the insulative layer are only filled part way up with metal. Then, the photoresist mask is removed thereby removing the metal layer deposited on it to leave only the metal in the insulative layer openings. Next, a second layer of metal is deposited over the first insulative layer and over the remaining metal in said openings, after which portions of the second metal layer over the insulative layer are removed to form a metallization pattern which is continuous with the metal in said openings.

Integrated fabrication method of forming connectors through insulative

In integrated circuit fabrication a method is provided involving the utilization of the same positive photoresist layer to form two different masks used in two separate etching steps. A positive photoresist layer is formed on a substrate, and portions of the positive photoresist layer are selectively exposed and developed to form the photoresist mask having a pattern of openings therethrough exposing the underlying substrate. Then, the substrate exposed in these openings is etched to form the pattern of recesses in the substrate corresponding to the openings. Next, portions of the remaining photoresist layer respectively adjacent to openings in the photoresist layer are exposed and developed to laterally expand such openings, after which the substrate exposed in these expanded openings is etched whereby the portions of the recesses underlying the original openings are etched deeper than the portions of the recesses underlying the expanded portions of said openings. The result is a two-level recess pattern. In accordance with an important aspect of the disclosure, the substrate being etched is a layer of electrically insulative material formed over an integrated semiconductor circuit member, and the deeper portions of the recesses are etched completely through the insulative layer to form holes which may be used for the passage of contacts to a semiconductor substrate where the insulative layer is directly on the substrate or as via holes when the insulative layer is formed between two layers of integrated circuit metallurgy.

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Hopewell Junction, NY, United States of America

Kenneth Chang