Oracle International Corporation

Xilinx, Inc.

Sun Microsystems, Inc.

Kenneth Chan

Chandrasekhar S Thyamagondlu

Ravi Nagarajarao Kurlagunda

Ravi S Sunkavalli

Sonal Santan

Hem C Neema

John R Feehrer

Ramaswamy Sivaramakrishnan

Julia D Harper

Matthew Cohen

Peter Dunlap

Lizhi Hou

Milton Shih

Chishein Ju

Rakesh Mehta

Kumarasamy Palanisamy

Karen Xie

Grace Y Nordin

Prashant Jain

A method and system for processing data are disclosed. A processor, in response to executing a software program, may write an entry in a work queue. The entry may include an operation, and a location of data stored in an input buffer, and a location in an output buffer to write processed data. The processor may also generate a notification that at least one entry in the work queue is ready to be processed. The data transformation unit may assign the entry to a data transformation circuit, and retrieve the data from the input buffer using the location. The data transformation unit may also perform to the operation on the retrieved data to generate updated data, generate a completion message in response to completion of the operation, and store the updated data in an output buffer. An interface unit may relay transactions between the processor and the data transformation unit.

Hardware accelerated data processing operations for storage data

A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

Streaming platform flow and architecture for an integrated circuit

An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.

Streaming platform architecture for inter-kernel circuit communication for an integrated circuit

A system and method for accurately modeling a fault log is provided for validating one or more elements of fault detection and logging logic for a real-time fault log of a digital system such as, for instance, a computer processor. The method includes injecting one or more known faults into a data path and/or a control path of the computer processor and spawning an individual tracking thread for each of the injected faults. The tracking threads may be synchronized at a predefined synchronization point that is selected as a function of a collective logging delay representing the time required for each of the injected faults to reach a real-time logging point within the computer processor. Once synchronized, the tracking threads may be input into a fault logging specification for fault behavior and/or system impact modeling and fault prioritization for use in generating a fault log model for comparison to the real-time fault log maintained within the computer processor.

Cycle accurate fault log modeling for a digital system

A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is injected into the virtual IC to trigger hardware error correction in the virtual IC and a software exception. A record of a type and a location of the soft error at the time of the injecting is created. The error log generated by hardware error correction is then compared with the record of injected error, the hardware error correction being part of the virtual IC. An IC design flaw is indicated when a discrepancy exists between the error log and the record of the injected error.

Method and system for verification of soft error handling with application to CMT processors

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Saratoga, CA, United States of America

Kenneth Chan