Silicon Graphics, Incorporated

Silicon Graphics International Corporation

Mips Technologies, Inc.

Kenneth C Yeager

David Zhang

Steven T Peltier

Steven C Miller

Martin M Deneroff

Mahdi Seddighnezhad

Gregory Marlan

Mazin S Khurshid

In an embodiment, a system includes a resource. The system also includes a first processor having a load/store functional unit. The load/store functional unit is to attempt to access the resource based on access requests. The first processor includes a congestion detection logic to detect congestion of access of the resource based on a consecutive number of negative acknowledgements received in response to the access requests prior to receipt of a positive acknowledgment in response to one of the access requests within a first time period.

Detection and control of resource congestion by a number of processors

In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.

Method for performing cache coherency in a computer system

In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Cache coherency is performed on appropriate caches in the computing system in accordance with the selected one of the plurality of coherency protocols. For a second memory transaction, another selection is made of the plurality of coherency protocols. The selected one of the coherency protocols for the second memory transaction may be the same as or different from the selected one of the plurality of coherency protocols for the first memory transaction.

A processor includes an active list to buffer instructions and their associated condition codes for processing. A mapping table in the processor maps a logical register associated with the instruction to a selected one of a plurality of unique physical registers. The selected unique physical register is used to hold a result according to execution of the instruction. An indication is provided to the mapping table when the selected unique physical register contains the result. The result is then moved to a fixed status register. The selected unique physical register is then returned for later reuse and the next consecutive physical register is selected for the next instruction such that physical registers are used in order. An indication is provided for output to inform whether the result is in the selected unique physical register or has been moved to the fixed status register.

Method and system for renaming registers in a microprocessor

An integrated circuit () includes a central processing unit (), an instruction cache (), a data cache (), and a trace recorder. The central processing unit () interacts with the instruction cache () and the data cache () in order to execute instructions. Information passed between the central processing unit (), the instruction cache (), and the data cache () not normally available for external analysis may be captured by the trace recorder () in response to various triggering events. The information captured by the trace recorder () may subsequently be provided to external test equipment in order to analyze the operation of the central processing unit () for failure correction.

Method and apparatus for recording trace data in a microprocessor based integrated circuit

In prefetching cache lines from a main memory to a cache memory, an array of memory locations to be prefetched is determined and a base address indicating a highest address in the array is identified as well as a loop index used to point to the first address in the array. A prefetch index, which is the loop index plus a latency/transfer value, is used to prefetch memory locations as the array is processed. After a memory location is prefetched and initialized, the loop index and the prefetch index are incremented. The prefetch index is compared to a threshold value. If the prefetch index is less than the threshold value, then the next memory location in the array is prefetched and the prefetch index is again incremented and compared to the threshold value. If the prefetch index is equal to or greater than the threshold value, then the prefetch instruction is converted to a no operation instruction to prevent memory locations outside of the array from being prefetched during the processing of the array.

Method and system for prefetching data

A cache memory includes a plurality of data memory blocks and a code memory block. Each data memory block has a plurality of storage locations and has a particular storage location identified by a same index value. The code memory block has a plurality of code values with a particular code value being associated with the same index value. The particular code value is operable to identify which ones of the particular storage locations associated with the same index value are locked to prevent alteration of contents therein. The particular code value is also operable to identify which particular storage location has been most recently used and which particular storage location has been least recently used of the particular storage locations associated with the same index value.

Cache memory for identifying locked and least recently used storage locations

An information capturing device ( ) includes a controller ( ) and a memory ( ). The controller ( ) partitions a memory space of the memory ( ) into a plurality of memory blocks ( ). The controller ( ) controls the storage of received information into a first set ( ) of the plurality of memory blocks ( ). The controller ( ) continues to store received information only in the first set ( ) of the plurality of memory blocks ( ) through reuse and recycle until a first triggering event occurs. In response to the first triggering event, the controller ( ) halts the storage of received information in the first set ( ) of the plurality of memory blocks ( ) and begins storing received information in a second set ( ) of the plurality of memory blocks ( ). When the second set ( ) of the plurality of memory blocks ( ) has reached its storage capacity, the controller ( ) begins storing received information in a third set ( ) of the plurality of memory blocks ( ). The controller ( ) continues to store received information only in the third set ( ) of the plurality of memory blocks ( ) through reuse and recycle until a second triggering event occurs. Information pertaining to the first triggering event is maintained in the first set ( ) and the second set ( ) of the plurality of memory blocks ( ).

Device and method for storing information in memory

An integrated circuit ( ) includes a central processing unit ( ), an instruction cache ( ), a data cache, ( ), and a trace recorder. The central processing unit ( ) interacts with the instruction cache ( ) and the data cache ( ) in order to execute instructions. Profile information passed between the central processing unit ( ), the instruction cache ( ), and the data cache ( ) not normally available for external analysis may be captured by the trace recorder ( ) in response to various execution points in a program being executed by the central processing unit ( ). The profile information captured by the trace recorder ( ) may subsequently be provided to external analysis equipment in order to analyze the operation of the central processing unit ( ) for study of program execution.

Method and apparatus for recording program execution in a microprocessor based integrated circuit

A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilities the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.

Cache memory with dual-way arrays and multiplexed parallel output

A translation lookaside buffer for detecting and preventing conflicting virtual addresses from being stored therein is disclosed. Each entry in the buffer is associated with a switch which can be set and reset to enable and disable, respectively, a buffer entry. A switch associated with an existing entry will be reset if such entry conflicts with a new buffer entry.

Translation lookaside buffer with virtual address conflict prevention

An address queue in a processor having the capability to track memory-dependencies of memory-access instructions is disclosed. The queue includes a first matrix of RAM cells that tracks a first dependency relationship between a plurality of instructions based upon matching virtual addresses (that identify a common cache set) and the order of instructions in the queue. To facilitate out-of-order instruction execution, dependencies may be tracked before virtual addresses are actually calculated based upon a presumption of dependency. Such dependency is dynamically corrected as addresses become available. The same comparison mechanism used to determine matching virtual addresses for the dependency relationship may also be used to read status bits of a cache set being accessed. The queue also includes a second matrix of RAM cells that tracks a second dependency relationship between a plurality of instructions based upon matching virtual addresses (that identify a common cache set, common doubleword and overlapping byte), the order of instructions in the queue and instruction type. Also disclosed is a method for processing memory instructions that uses a single comparison step between first and second virtual addresses (calculated from instructions) to indicate a dependency relationship between the instructions and to read memory status bits. The status bits are read to determine accessibility of a way within an addressed cache set.

Address queue

Redundant mapping tables for use in processors that rename registers and perform branch prediction is presented. The redundant mapping tables include a plurality of primary RAM cells coupled to a plurality of redundant RAM cells. In the event of a branch instruction, the redundant RAM cells can save the contents of the primary RAM cells in a single clock cycle before the processor decodes and executes subsequent instructions along a predicted branch path. Should the branch instruction be mispredicted, the redundant cells can restore the primary RAM cells in a single clock cycle. A branch stack, coupled to the redundant mapping tables, updates restored mapping tables with changes made for preceding instructions that were decoded in parallel with the branch instruction. A plurality of levels of redundant RAM cells may be used to enable the nesting of a plurality of branch predictions at any one time.

Growing community of inventors

Sunnyvale, CA, United States of America

Kenneth C Yeager