Motorola Corporation

Kenneth C Weng

Chia-Shiann Weng

Paul M Astrachan

Donald C Anderson

Jeffrey D Ganger

Peter C Curtis

Walter U Kuenast

Kevin Yun-kang Wu

Der-Gao Lin

Christopher Sterling Lohn

Chia S Weng

A method of forming a stacked capacitor structure in a semiconductor device, having metal electrode plates. After depositing the bottom electrode layer (26) and the dielectric layer (28) of the capacitor, a rough patterning step is carried out to roughly pattern or shape the bottom electrode layer and the dielectric layer, and to expose the underlying interlayer dielectric (18). A top electrode layer (32) is then blanket deposited, and another, more precise etching step is carried out to form the final shape of the capacitor element, while leaving behind a portion of the top electrode layer on the interlayer dielectric, which forms a metal interconnect (36). In one embodiment, the electrode layers are comprised of materials having a conductivity greater than doped silicon (either poly or monocrystalline), such as a metal.

Method for forming a semiconductor device having a capacitor structure

A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field.

Data processor with an efficient bit move capability and method therefor

Tone detection may be accomplished by receiving an in-phase signal component 203 and a quadrature signal component 204. These components are then sampled to produce a plurality of sampled in-phase signal components 207 and a plurality of sampled quadrature signal components 208. The sampled in-phase signal components 207, or the sampled quadrature signal components 208, are then shifted by a pre-determined phase angle to produce a plurality of shifted components. Having shifted these signals, the shifted signals, or at least a set of them, are compared with the opposite non-shifted sampled signals, or a set thereof. When each of the shifted signal components substantially match the opposite non-shifted signal components, a tone signal is being received.

Method and apparatus for detecting reception of a tone signal

An integrated circuit identification device (10) includes a plurality of inverters (12-16), a first bus (24), an address bus (26), a plurality of drivers (18-22), a pre-charge circuit (28) and an identification code access (30). Each inverter (12) includes a P-channel FET (32-36) and an N-channel FET (38). An identification code is written to the device (10) by selectively breaking down the gate-well dielectric layer (112) of the N-channel FET which permanently alters the FET. When the address bus provides a read signal to the gate drivers, each N-channel FET that has been altered will be unable to turn on, thus the precharging of the P-channel FET keeps the output of the inverter at a logic '1'. N-channel FETs that have not be altered will be on when the read signal is provided, thus providing a logic '0'.

Integrated circuit identification apparatus and method

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Austin, TX, United States of America

Kenneth C Weng