Imagination Technologies Limited

Kenneth C Rovers

Yoong Chert Foo

Rostam King

Yoong-Chert Foo

Faizan Nazar

A decoder decodes a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format. A parameter decode unit decodes configuration data for the received block of texture data, a colour decode unit decodes colour endpoint data for the plurality of texels in dependence on the configuration data, a weight decode unit decodes interpolation weight data for each of the plurality of texels in dependence on the configuration data, and at least one interpolator unit calculates a colour value for each of the plurality of texels using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data. At least one of the parameter decode unit, colour decode unit and weight decode unit decodes intermediate data from the received block that is common to the decoding of a subset of texels of that block and uses that decoded data as part of the decoding of at least two of the plurality of texels.

Multi-output decoder for texture decompression

A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew−1), bitwidth(iw−2−s)}≤k≤(ew−1) where s=1 for a signed floating point number and s=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

Floating point to fixed point conversion

A method of performing anisotropic texture filtering includes generating one or more parameters describing an elliptical footprint in texture space; performing isotropic filtering at each of a plurality of sampling points along a major axis of the elliptical footprint, wherein a spacing between adjacent sampling points of the plurality of sampling points is proportional to √{square root over (1−η)} units, wherein η is a ratio of a major radius of an ellipse to be sampled and a minor radius of the ellipse to be sampled, wherein the ellipse to be sampled is based on the elliptical footprint; and combining results of the isotropic filtering at the plurality of sampling points with a Gaussian filter to generate at least a portion of a filter result.

Anisotropic texture filtering by combining results of isotropic filtering at a plurality of sampling points with a gaussian filter

A binary logic circuit for performing an interpolation calculation between two endpoint values Eand Eusing a weighting index i for generating an interpolated result P, the values Eand Ebeing formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values Cand Crespectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values Cand Cusing the weighting index i to generate a first intermediate interpolated result C; and combinational logic circuitry configured to receive the interpolated result Cand to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=└((C<<8)+C+32)/64┘ when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=└((C<<8)+128·64+32)/64┘ when the interpolated result is to be compatible with an sRGB colour space.

ASTC interpolation

A binary logic circuit performs an interpolation calculation between two endpoint values Eand Eusing a weighting index i for generating an interpolated result P, the values Eand Ebeing formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values Cand Crespectively, the colour endpoint values Cand Cbeing low-dynamic range (LDR) or high dynamic range (HDR) values. An interpolation unit performs an interpolation between the values Cand Cusing the index i to generate a first intermediate interpolated result C; combinational logic circuitry receives the result Cand performs logical processing operations to calculate the interpolated result P according to the equation: (1) P=└((C<<8)+C+32)/64┘ when the interpolated result is not to be compatible with an sRGB colour space and the colour endpoint values are LDR values; (2) P=└((C<<8)+128·64+32)/64┘ when the interpolated result is to be compatible with an sRGB colour space and the colour endpoint values are LDR values; and (3) P=(C+2)>>2 when the colour endpoint values are HDR values.

An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.

Method and circuit for performing error detection on a clock gated register signal

An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.

A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data. At least one of the parameter decode unit, colour decode unit and weight decode unit are configured to decode intermediate data from the received block that is common to the decoding of at least a subset of texels of that block and to use that decoded intermediate data as part of the decoding of at least two of the plurality of texels from the received block of texture data.

A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.

Multiplexing between different processing channels

A binary logic circuit for performing an interpolation calculation between two endpoint values Eand Eusing a weighting index i for generating an interpolated result P, the values Eand Ebeing formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values Cand Crespectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values Cand Cusing the weighting index i to generate a first intermediate interpolated result C; and combinational logic circuitry configured to receive the interpolated result Cand to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=&#x2514;((C&#x3c;&#x3c;8)+C+32)/64&#x2518; when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=&#x2514;((C&#x3c;&#x3c;8)+128&#xb7;64+32)/64&#x2518; when the interpolated result is to be compatible with an sRGB colour space.

A binary logic circuit for performing an interpolation calculation between two endpoint values Eand Eusing a weighting index i for generating an interpolated result P, the values Eand Ebeing formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values Cand Crespectively, the colour endpoint values Cand Cbeing low-dynamic range (LDR) or high dynamic range (HDR) values, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values Cand Cusing the weighting index i to generate a first intermediate interpolated result C; combinational logic circuitry configured to receive the interpolated result Cand to perform one or more logical processing operations to calculate the interpolated result P according to the equation: (1) P=&#x2514;(C&#x3c;&#x3c;8)+C+32)/64&#x2518; when the interpolated result is not to be compatible with an sRGB colour space and the colour endpoint values are LDR values; (2) P=&#x2514;(C&#x3c;&#x3c;8)+128.64+32)/64&#x2518; when the interpolated result is to be compatible with an sRGB colour space and the colour endpoint values are LDR values; and (3) P=(C+2)&#x3e;&#x3e;2 when the colour endpoint values are HDR values.

A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2&#x2212;1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes an offset unit configured to offset the exponent of the floating point number by an offset value equal to (iw&#x2212;1&#x2212;s) to generate a shift value sof sw bits given by s=(B&#x2212;E)+(iw&#x2212;1&#x2212;s), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format; a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the shifter being configured to right-shift the input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2&#x2212;1, iw&#x2212;1&#x2212;s)+min(2&#x2212;2, fw)]&#x2264;k&#x2264;sw, where s=1 for a signed floating point number and s=0 for an unsigned floating point number.

Floating point to fixed point conversion using exponent offset

A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2&#x2212;1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew&#x2212;1),bitwidth(iw&#x2212;2&#x2212;s)}&#x2264;k&#x2264;(ew&#x2212;1) where s=1 for a signed floating point number and s=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.

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St. Albans, United Kingdom

Kenneth C Rovers