Intel Corporation

Kenneth C Holland

Raman Nayyar

Jasmin Ajanovic

David M Lee

Narendra S Khandekar

Susan S Meredith

Dahmane Dahmani

A block of data may be transferred to memory through a plurality of write operations, where each write operation is preceded by a protocol request and a protocol response. A plurality of protocol requests issued in a first order may elicit a corresponding plurality of protocol responses in a second order, and the write operations may be performed in yet a third order. Chipsets implementing the data write methods are also described and claimed.

Method and apparatus for memory write performance optimization in architectures with out-of-order read/request-for-ownership response

A synchronizing circuit translates signals in a slow clock domain into a fast clock domain. The frequency of the slow clock is a submultiple of the fast clock frequency. A synchronizing pulse signal is developed at the frequency of the slow clock, but is phase synchronized to the fast clock. The synchronizing pulse signal is employed to gate the signal in the slow clock domain so that it is synchronized in the fast clock domain. In a system where the ratio between the fast clock frequency and slow clock frequency is determined by a frequency divisor signal, a snooping circuit is employed to capture the frequency divisor signal to achieve rapid synchronization between the clock domains.

Method and apparatus for translating signals between clock domains of

A computer system includes a bus, a first bus device, a core circuit and a second circuit. The first bus device is coupled to the bus and adapted to finish a first indication of data to a portion of a bus beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus beginning at another clock cycle. The second circuit is coupled to the bus and is adapted to receive an indication of a selected latency time. The second circuit is also adapted to transfer the data to the core circuit in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.

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Hillsboro, OR, United States of America

Kenneth C Holland