Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Kenneth C Haren

Mark A Schmisseur

Sivakumar Radhakrishnan

Sin Sim Tan

Pankaj Kumar

Michael T Klinglesmith

Bradley A Burres

Eric Dahlen

Thomas M Slaight

Brian M Leitner

Geetani R Edirisooriya

Marc Tim Jones

David C Lee

Matthew R Wilcox

Saptarshi Mondal

Vinodh Gopal

Wajdi K Feghali

Thomas C Brown

Tuan M Quach

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.

Presentation of direct accessed storage under a logical drive model

Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality of exclusive OR logic include first exclusive OR logic and second exclusive OR logic. First Galois Field multiplier logic multiplies a first output from the first exclusive OR logic and a first portion of a plurality of portions of the input data. Second Galois Field multiplier logic multiplies a second output from the second exclusive OR logic and a second portion of the plurality of portions of the input data. Other embodiments are also disclosed and claimed.

Enhanced cyclical redundancy check circuit based on galois-field arithmetic

Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

An interrupt controller includes conductors for receiving interrupt request signals, a memory, a register and control logic. Each of the interrupt request signals are capable of indicating an interrupt request. The memory is capable of storing information about the interrupt request signals, and the register is writable to identify a set of locations of the memory for scanning. The control logic scans the set of locations for interrupt requests and does not scan other locations of the memory for interrupt requests. In some cases, the number of interrupt request signals are exceeds the number of locations. For these cases, information about selected interrupt signals are stored in the locations.

Interrupt controller

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Portland, OR, United States of America

Kenneth C Haren