Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Kenneth C Duisenberg

Justin E York

Thomas Hanson

Rajeev Grover

Loren M Koehler

Stephen B Lyle

Ivan Farkas

Michael J Allen

Robert William Dobbs

Andrew Christopher Walton

Kevin Edward Boyum

John E Nolan

Kenneth Nicholas Konesky

Tamra I Perez

Nehal K Patel

Joshua Kennon Crechriou

A management processor includes a peripheral identifier to identify a peripheral device installed in a computing device. The management processor also includes a code retriever to receive management code from the peripheral device. The management processor also includes a code executor to execute the management code to provide, at the management processor, a management application programming interface (API) accessible by a remote client to manage the peripheral device, the remote client being external to the management processor.

Management processor using code from peripheral device

Various examples described herein provide for monitoring a peripheral device by data imported from the peripheral device. The peripheral data may comprise a script associated with monitoring or managing the peripheral device, or descriptive data describing a set of monitor values on the peripheral device.

Monitor peripheral device based on imported data

Various examples described herein provide for a management processor that reads a registration script from a peripheral device, and uses the script to act in proxy to register the peripheral device as a data provider on the management processor. Once a peripheral device is registered as a data provider on the management processor, the management processor can permit the peripheral device to host a management resource on the management processor. By accessing the hosted management resource through the management processor, a client can manage, monitor, or control the peripheral device.

Management processor executing peripheral device registration script

Various embodiments of a method [] of distributing configuration information within a predefined set of conjoined blades of a blade partition are described. In one embodiment, a configuration rule at a database for a predefined set of conjoined blades of a blade partition is accessed, wherein conjoined blades within the blade partition are coupled with management processors []. A portion of the configuration rule is compared with a hardware configuration of the blade partition []. The portion of the configuration information is an identification of the conjoined blades []. When the portion of the configuration rule correlates with the hardware configuration, the configuration rule is provided to the management processors of the blade partition [

Domain management processor

Systems, methods and computing components are provided for dynamically reallocating a plurality of computing components among one or more logical partitions. A first computing component that is allocated to a first partition may have a management processor. A second computing component may be allocated to a second partition. The management processor of the first computing component may be configured to reallocate the first computing component to a third partition without affecting the second computing component.

Dynamically reallocating computing components between partitions

Systems, methods and computing components are provided for allocating a plurality of computing components among one or more logical partitions. Each of the plurality of computing components may have a management processor that is configured to assume a role among management processors of a partition. Each management processor may then cooperate with other management processors of the partition to control resources of the partition.

Management processors cooperating to control partition resources

Method and system of error logging. At least some of the illustrative embodiments are methods including detecting assertion of an error pin by a processor system, (comprising at least a main processor and a chipset, the assertion of the error pin an indication to reboot the processor system) the detecting by a reset circuit, notifying a management processor (distinct from the main processor) that the error pin is asserted (the notifying by the reset circuit), writing to a plurality of registers in the chipset (the writing by the management processor), de-asserting a reset pin of the main processor, and then executing by the main processor an error-handling code to generate an error log.

Method and system of error logging

A computer system provides for connecting consecutively positioned modules to operate collectively as server. Each module calculates a modulo difference between its position and that of a module serving as a clock source; each module selects a clock input as a function of the result of that calculation.

Clock source selection for modular computer system as a function of modulo difference

Method and apparatus for synchronizing a software buffer index with an unknown hardware buffer index. Specifically, a method of processing data is disclosed comprising synchronizing a software buffer index to a hardware buffer index. The method sequentially searches through a plurality of buffers containing data to find a second buffer with unprocessed data. The method is implemented when the software buffer index points to a first buffer containing processed data. Thereafter, the software buffer index is reset to the next available buffer having processed data following the second buffer.

Method and apparatus for synchronizing a software buffer index with an unknown hardware buffer index

Embodiments of the invention provide a method and an apparatus for utilizing a microcontroller to provide an automatic order and timing power and reset sequencer. A first inter-integrated circuit (I2C) register table containing a modifiable system power-up sequence is accessed. An automatic system power-up operation is then performed in the order of the power-up sequence defined by the first I2C register table.

Method and apparatus for utilizing a microcontroller to provide an automatic order and timing power and reset sequencer

Method and apparatus of separating packets. Specifically, a method of separating data packets in a memory buffer is disclosed. The method locates a memory buffer containing a pre-selected address at a buffer header of the memory buffer. A first data packet containing the buffer header is separated from a remaining part of the memory buffer. The first data packet is associated with a first packet length. The method then searches the remaining part of the memory buffer to locate a plurality of packet headers associated with a plurality of concatenated data packets. Each of the plurality of packet headers contains the pre-selected address. The method then separates the plurality of concatenated data packets, that is associated with a plurality of concatenated packet lengths, for processing.

Method and apparatus for separating data packets in a memory buffer

Techniques are provided for assigning a device to a desired network. In one embodiment, the device is connected via a network switch to the network. A value of a configurable parameter corresponds to a data speed that would be used to transfer the data between the device and the network. To assign the device to the network, the value of the parameter corresponding to a desired speed is set in the network circuitry of the device. The network switch, interfaces with the device, detects the speed, and, based on this speed, assigns the device to a corresponding network. Additionally, the switch can assign the data duplex based on a value of a configurable duplex parameter set in the network circuitry.

Growing community of inventors

Roseville, CA, United States of America

Kenneth C Duisenberg