Intel Corporation

Kenneth C Creta

Robert G Blankenship

Sujoy Sen

Gregory Cummings

Jasmin Ajanovic

William T Futral

Sivakumar Radhakrishnan

Sridhar Muthrasanallur

Robert T George

Tony S Rand

Akhilesh Kumar

Lily Pao Looi

Aaron T Spink

Manoj Khare

Bradford B Congdon

Debendra Das Sharma

Mohan J Kumar

Yen-Cheng Liu

Joseph A Bennett

Ganapati Srinivasa

Bahaa Fahim

Brian S Morris

Lance E Hacking

Michelle C Jen

Keshavan K Tiruvallur

Suresh S Chittor

Geeyarpuram N Santhanakrishnan

Balint Fleischer

David C Lee

Siva Balasubramanian

Sridhar Muthrasanalluar

Mathew A Lambert

David J Harriman

Robert J Greiner

Randy B Osborne

Gary A Solomon

Kai Cheng

David M Lee

Herbert H J Hum

Elliot D Garbus

Robert J Miller

Buderya S Acharya

Doug Moran

Vasudevan Shanmugasundaram

Deepak Ramachandran

Thai Q Nguyen

Duane January

Mike Bell

Jason W Horihan

Gregory D Cummings

A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

Sharing memory and I/O services between nodes

A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed.

Providing common caching agent for core and integrated input/output (IO) module

Methods and apparatuses for flushing write-combined data from a buffer within a memory to an input/output (I/O) device.

Methods and apparatuses for flushing write-combined data from a buffer

Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device.

Write combining protocol between processors and chipsets

A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

Stream priority

Techniques to broadcast a message across a point-to-point network are described. More particularly, some embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect. Other embodiments are also disclosed.

Techniques for broadcasting messages on a point-to-point interconnect

A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub.

Method and apparatus for the synchronization of distributed caches

Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to non-posted transactions. One embodiment further provides for halting an inbound ordering queue of the first I/O hub with regard to non-posted transactions in response to the first flush command and flushing a non-posted transaction from an outgoing buffer of the first I/O hub to a second I/O hub while the inbound ordering queue is halted with regard to non-posted transactions.

Multi-node chipset lock flow with peer-to-peer non-posted I/O requests

A technique to broadcast a message across a point-to-point network. More particularly, embodiments of the invention relate to broadcasting messages between electronics components within a point-to-point interconnect.

Technique for broadcasting messages on a point-to-point interconnect

Growing community of inventors

Gig Harbor, WA, United States of America

Kenneth C Creta