International Business Machines Corporation

Other

Massachusetts Institute of Technology

Infineon Technologies LLC

Kenneth C Arndt

Jack Allan Mandelman

Louis L Hsu

Chandrasekhar Narayan

Jeffrey P Gambino

Carl John Radens

Dureseti Chidambarrao

Richard Anthony Conti

Axel Christoph Brintzinger

Laertis Economikos

K Paul Muller

David M Dobuzinsky

Peter D Hoh

David Lachtrupp

Toshiaki Kirihata

Ravikumar Ramachandran

Michael John Cima

Ronald J Schutz

Dirk Tobben

Donna Rizzone Cote

Thomas S Rupp

Gabriel Daniel

Rainer F Schnabel

Senthil K Srinivasan

Lynne M Svedberg

A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.

Electrically blowable fuse with reduced cross-sectional area

A semiconductor device has a first conductor and a second conductor for fuse terminals. A fuse portion is disposed on a different level relative to both the first conductor and the second conductor. A first contact connects the fuse portion to the first conductor, and a second contact connects the fuse portion to the second conductor.

Multi-level fuse structure

A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

Mixed fuse technologies

A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.

Sublithographic fuses using a phase shift mask

A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.

Manufacturing of cavity fuses on gate conductor level

The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

Integrated circuits having reduced stress in metallization

A process for selective electroless plating onto a substrate, including providing a substrate having at least a catalytic surface; providing a plating gel comprising a carrier vehicle, an electroless platable metal compound capable of providing metal ions to the carrier vehicle at a specific pH, a reducing agent, and a polymeric thickening agent; applying said plating gel to the substrate surface in a selected pattern, and inducing plating of said metal on the substrate surface in said selected pattern. A stabilizer, and/or buffering and/or organic chelating agent, and/or surfactant and/or a humectant may be included in the plating gel. Preferably the metal compound is a gold complex, and the substrate is aluminum nitride.

Selective substrate metallization

Method of producing sulithographic fuses using a phase shift mask

A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.

Semiconductor structure including a conductive fuse and process for

A programmable/reprogrammable fuse arrangement that includes two fuse links provided each with an output port and an exclusive-or gate connected to the output port of each of the two fuses, wherein the fuse arrangement is reprogrammed by successively blowing both of the two fuse links is described. The programmable/reprogrammable fuse arrangement can be extended to a plurality of fuses and cascaded exclusive-ORs such that each fuse link provides one leg of the gate and the previous stage, the second. Thus, for N fuse links and N exclusive-ORs, the fuse arrangement thus formed can be reprogrammed a total of N times by sequentially blowing one fuse link at a time. The arrangement ceases to be reprogrammable once all the fuse links have been blown. The reprogrammable fuse arrangement is of particular importance for semiconductor memories and microprocessors, as for instance, for bringing in-line redundancy units attached to a fuse link.

Programmable/reprogrammable fuse

Method for reducing stress in the metallization of an integrated circuit

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Fishkill, NY, United States of America

Kenneth C Arndt