Microsoft Technology Licensing, LLC

Kenneth Bryant Pierce

Ho-Yuen Chau

Andrew James Edwards

Darek Josip Mihocka

Wen-Ke Chen

Sanjay Bhansali

Ronald C Murray

Stuart D De Jong

Program execution can be monitored and recorded for later playback. Certain state changes that can be predicted via a virtual processor during playback need not be recorded, so a compressed recording can be stored. To facilitate random access with respect to time during playback, key frames can be stored within the compressed recording. An index mechanism can associate key frames with particular memory addresses. Additionally, a snapshot of values for memory addresses can be used to further facilitate determining the value of a memory address without having to simulate execution. Multiprocessor executions can be supported, and playback can be done on a machine type different from that on which recording took place.

Compressed program recording

A method used for walking forward through a binary image of a procedure to identify a return instruction, and while walking forward through the binary image, identifying a set of instructions that affect the distance to a return address stored in the stack. After calculating distance structure variables based on the set of instructions, and using the distance structure variables to update the stack pointer and the instruction pointer, returning to walk forward through the binary image pointed to by the updated instruction pointer. This continues until the stack is empty, and then a list of all instruction pointers are returned, as a call chain. An additional optimization includes caching a list on instruction pointer addresses with already computed distance structure variables.

Forward walking through binary code to determine offsets for stack walking

Tools and methods are described herein for discovering race condition errors in a software program. The errors are discovered by deliberately causing a processor executing the test program to switch threads at intervals other than normally scheduled by an operating system. The thread switching is caused upon occurrence of selected events. The intervals may be selected automatically or with user input. Furthermore, thread switching may be caused during conditions more likely to cause race condition errors. For example, thread switches may be caused between threads that share control of a memory device or while the processor is executing instructions related to synchronization tools (e.g. locks, mutex, etc.).

Tools and methods for discovering race condition errors

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Kenneth Bryant Pierce