Intel Corporation

Other

Kenneth B Oliver

William A Hobbs

Nitin V Sarangdhar

Tsvika Kurts

Gerald A Budelman

Stephen J Peters

Jonathan C Lueker

Douglas Raymond Moran

Dean Warren

Thomas C Brown

Doug Boyce

Bronson Salcedo

Pierre M Brasseur

A weather and bullet proof display system includes a casing that is nested within a headstone and has an opening formed therein. Solar panels are mounted on the headstone. A bullet proof shield is conjoined to the casing within the opening. A display screen is disposed behind the shield. A mechanism for converting solar energy to electrical energy is coupled to the solar panels and housed within the casing. A 12-volt rechargeable battery is coupled to the energy converting mechanism. A mechanism is included for converting a first DC voltage input level to a second DC voltage level, which is coupled to the solar energy converting mechanism. A system board is coupled to the DC voltage level converting mechanism and includes a mechanism for contemporaneously emitting a prerecorded audio and video output. Speakers are nested within the headstone and are coupled to the DC voltage level converting mechanism.

Weather-proof and tamper-proof audio/video display system and associated housing for outdoor use

In order to recover phase information, data transmitted at a first frequency is over-sampled using a clock at a second frequency, n times per bit time to obtain n samples. The n samples are used to detect the transitions between two logic levels in said transmitted data which are stored in groups of m sets of said n edge results which are, in turn output at a clock frequency which is the second frequency divided by m, for further processing.

Data recovery method and apparatus

A system for generating transactions on a bus includes at least one instruction memory storing predefined bus stimuli instructions and at least one phase generator coupled between the bus and the instruction memory for providing signals to the bus in response to the instruction memory.

Testing a bus using bus specific instructions

Arrangements for maintaining out-of-order queue cache coherency and for prevention of memory write starvation.

Arrangements for out-of-order queue cache coherency and memory write starvation prevention

An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.

Bus patcher

Growing community of inventors

Newberg, OR, United States of America

Kenneth B Oliver