Sandisk Enterprise IP LLC

Bose Corporation

Sandisk Technologies Inc.

Kenneth B Delpapa

Gregg Steven Lucas

Robert W Ellis

Michael B Nussbaum

Andrew Ferencz

Thomas A Froeschle

George Nichols

Lace J Herman

Jay N Teixeira

Charles N Gibson

Systems, methods and/or devices are used to reduce anomalous charging current by selectively shunting biasing current away from a control terminal of a controlled device that conducts the charging current during a charging mode. In some embodiments, a power-control circuit includes: (1) a controlled device with a first terminal coupled to a power-supply node, a second terminal to provide a first output voltage, and a control terminal; (2) a current source to provide a biasing current to the control terminal of the controlled device during a charging mode; and (3) a selective current shunt to shunt a portion of the biasing current away from the control terminal of the controlled device in response to a determination that a charging current through the first and second terminals of the controlled device satisfies a threshold during the charging mode.

Voltage slew rate throttling for reduction of anomalous charging current

The various embodiments described herein include systems, methods and/or devices used to enable power inrush management of storage devices (e.g., DIMM devices). In one aspect, the method includes, for at least one storage device populated in a slot of a plurality of storage device slots, the plurality of storage device slots configured to be populated by two or more storage devices: (1) detecting a unique location associated with the storage device, (2) determining a time delay for the storage device in accordance with the unique location associated with the storage device, and (3) delaying at least one power-on operation of the storage device by the time delay for the storage device.

Power inrush management of storage devices

The various implementations described herein include systems, methods and/or devices used to enable performing supervisory functions for a dual in-line memory module (DIMM), at a controller in the DIMM. The method includes upon power-up, determining a power supply voltage provided to the DIMM. In accordance with a determination that power supply criteria are satisfied, the method includes: (1) performing one or more power-up operations, including initiating a usage counter, (2) monitoring a temperature of the DIMM, (3) monitoring the DIMM for occurrence of one or more of a set of predetermined trigger events, and (4) in response to detecting one of the set of predetermined trigger events, logging information corresponding to the detected predetermined event.

DIMM device controller supervisor

A power supply injects a series of 'tickle' pulses into a pulse width modulated (PWM) controller to induce the controller to generate PWM pulses at a minimum switching frequency, preferably one that is super-sonic (especially for audio applications). The switching frequency may also be selected or controlled such that it avoids resonances in the power supply. The 'tickle' pulses may be clocked by the same clock that times the PWM controller, and they may be shaped to help ensure that the power supply maintains some regulation during low-load conditions.

Power supply with tickle pulse injection

The various implementations described herein include systems, methods and/or devices used to enable power sequencing and a data hardening module in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is lower than an under-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is lower than the under-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device.

Power sequencing and data hardening architecture

The various embodiments described herein include systems, methods and/or devices used to enable power fail latching based on monitoring multiple power supply voltages in a storage device. In one aspect, the method includes: (1) determining whether a first power supply voltage provided to the storage device is out of range for a first time period, (2) determining whether a second power supply voltage provided to the storage device is out of range for a second time period, and (3) in accordance with a determination that at least one of the first power supply voltage is out of range for the first time period and the second power supply voltage is out of range for the second time period, latching a power fail condition.

Power fail latching based on monitoring multiple power supply voltages in a storage device

The embodiments described herein include a method and device for adjusting trip points within a storage device. The method includes: obtaining one or more configuration parameters; and based on the one or more configuration parameters, determining a trip voltage. The method also includes comparing the trip voltage with an input voltage. The method further includes triggering a power fail condition in accordance with a determination that the input voltage is less than the trip voltage.

System and method for adjusting trip points within a storage device

The various implementations described herein include systems, methods and devices used to protect data in a storage device. In one aspect, a method includes, performing a soft power fail operation on a section of the device, the operation including: (1) signaling a power test condition to a first controller on the storage device; (2) providing one or more controllers with power from an energy storage device, where the energy storage device is distinct from a power supply used during normal operation; (3) signaling a power fail condition to the one or more controllers on the storage device, where the one or more controllers communicate with the first controller and correspond to said section of the storage device, and where, in response to the power fail condition, each of the one or more controllers performs a data hardening operation; and (4) resuming normal operation on said section of the storage device.

Power failure architecture and verification

The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, a method includes, in response to a first signal received by the storage device, performing a soft power fail operation on a first section of the storage device. The soft power fail operation including: (1) signaling a power fail condition to a first plurality of controllers on the storage device, where the first plurality of controllers correspond to the first section of the storage device, (2) transferring data held in volatile memory of the storage device to non-volatile memory of the storage device, and (3) removing power from the first plurality of controllers.

Simulated power failure and data hardening

The various implementations described herein include systems, methods and/or devices used to protect data in a storage device. In one aspect, a method includes (1) powering a power control processor (PCP) (also sometimes called a storage-level microcontroller) using a first input voltage, (2) while the PCP is powered using the first input voltage: (a) operating the PCP in a first mode, and (b) enabling charging of an energy storage device, (3) after achieving a predefined internal state, which includes the energy storage device charged to a predefined level, powering the PCP using a power supply voltage distinct from the first input voltage, and (4) while the PCP is powered using the power supply voltage, operating the PCP in a second mode, where the PCP operates at a higher performance level in the second mode than in the first mode.

Startup performance and power isolation

The various embodiments described herein include systems, methods and/or devices used to enable dynamic brownout adjustment in a storage device. In one aspect, the method includes: (1) obtaining a set of power tolerance settings, the set of power tolerance settings used for determining whether one or more power supply voltages provided to the storage device are out of range, (2) in response to a predefined trigger, adjusting the set of power tolerance settings in accordance with one or more parameters of the storage device, (3) determining, in accordance with the adjusted set of power tolerance settings, whether the one or more power supply voltages are out of range, and (4) in accordance with a determination that the one or more power supply voltages are out of range, latching a power fail condition.

Dynamic brownout adjustment in a storage device

The various implementations described herein include systems, methods and/or devices used to enable power sequencing and data hardening in a storage device. In one aspect, the method includes determining whether a power supply voltage provided to the storage device is higher than an over-voltage threshold. The method further includes, in accordance with a determination that the power supply voltage is higher than the over-voltage threshold, performing a power fail operation, the power fail operation including: (1) signaling a power fail condition to a plurality of controllers on the storage device, (2) transferring data held in volatile memory to non-volatile memory, and (3) removing power from the plurality of controllers on the storage device.

Hard power fail architecture

An electrical apparatus to sense current through a load includes a first input terminal having a first input voltage relative to a reference, a second input terminal having a second input voltage relative to the reference, a first load terminal of the load having a first load voltage relative to the reference, a second load terminal of the load having a second load voltage relative to the reference, a first current sensing element connected between the first input terminal and the first load terminal and a second current sensing element connected between the second input terminal and the second load terminal. A first sense voltage is determined by a relationship between the first input voltage and the second load voltage and a second sense voltage is determined by a relationship between the second input voltage and the first load voltage.

Audio system with synthesized positive impedance

An audio system including an audio power amplifier, a transducer electrically connected to the audio power amplifier, an enclosure coupled to the transducer, and a secondary resonant element coupled to the enclosure. An electrical feedback signal representative of the transducer current is negatively fed back to the audio power amplifier to synthesize a positive output impedance.

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Natick, MA, United States of America

Kenneth B Delpapa