Peco Ii, Inc.

International Business Machines Corporation

Celestica, Inc.

Kenneth Andrew Wallace

Gueorgui I Mantov

Garey George Roden

Stephen F Newton

James Jens Hansen

John Roller

Terry Chester Lahr

Jon Drew Karnes

Robert J Huljak

Michael Shane Elmore

David Robert Fletcher

John Michael Gallagher

Methods and apparatus are disclosed for achieving load balance between parallel inverters in an AC power supply. Load balancing reduces undesirable cross conduction current between the parallel inverters. Load balancing and the resulting reduction in cross conduction current are achieved without the need for common control circuitry between the parallel inverters. Thus, the single-fault protection offered by redundant parallel inverters is not compromised by the disclosed load balancing techniques.

Methods and apparatus for load sharing between parallel inverters in an

A noise suppression circuit for use with a DC/DC converter having an output and an input responsive at least in part to the output of the converter is provided. The noise suppression circuit includes multiple parallel feedback loops, wherein the first feedback sets the steady state nominal output voltage, the second feedback loop prevents the output voltage from exceeding a predefined high voltage level, and the third feedback loop prevents the output voltage from decreasing below a predefined low voltage level. In some embodiments, the first, second, and third feedback loops comprise a operational amplifier, a diode, and an internal feedback loop, wherein the internal feedback loops of each of these loops share a common node. The common node configuration provides the circuit with quick transitions between output voltage states and dynamic regulation of the DC/DC converter output voltage.

Inverter input noise suppression circuit

A FET drive circuit is disclosed. The disclosed drive circuit develops a unipolar voltage from a bi-polar source voltage and facilitates fast turn-off of the driven FET. Preferably, the drive circuit includes a first diode having a first reverse recovery time, a transistor, and a second diode having a second reverse recovery time which is longer than the first reverse recovery time.

Transformer coupled FET drive circuit

A rectifying circuit comprising first and second current doublers is disclosed. In some embodiments, the first and second current doublers are connected in series. In other embodiments, the current doublers are connected in parallel. In phase pairs of inductors can share a common core to reduce parts and ensure voltage balance.

Dual coupled current doubler rectification circuit

A composite power supply comprises a master ZVS power supply and a slave ZVS power supply. Using a phase lock loop circuit, the composite power supply detects a phase relationship between switching of the first switch and switching of the second switch, and adjusts timing of switching of the second switch if the first switch and the second switch are not being switched at a predetermined phase relationship with each other. The outputs of the two power supplies are connected together. Thus, the master power supply contributes approximately half the output power and precision control on the output/load voltage while the slave power supply contributes approximately half the output power.

Zero voltage switching supplies connected in parallel

A planar transformer wherein a conformal dielectric epoxy composition is provided on the planes containing the primary and secondary windings to encapsulate the windings and to insulate the windings from the perimeter of each plane to prevent the primary windings from electrically contacting the secondary windings around the edges of the planes. Also, a conformal dielectric epoxy composition separates the plane with the primary windings from the plane with the secondary windings from primary and secondary circuits directly and below windings.

Planar transformer and method of manufacture

A DC to DC power converter having reduced switching loss for operation at high frequencies. As disclosed, a buck, or forward, converter includes a first FET as the switching device in series with an inductor and a second FET as the flywheel device. At the common node to which the two FET's and the inductor are connected, there is sufficient capacitance that the FET's may be turned off without appreciable voltage change across the FET's. The value of the inductor is chosen, with respect to the input and output voltages and frequencies of operation involved, to insure that the inductor current polarity reverses each cycle, raising the node voltage to the level of the input voltage, substantially eliminating turn-on losses of the first FET. Control circuitry is provided for regulation of the power converter to control the peak-to-peak current in the inductor and to insure that at least a selected minimum value of the inductor current is present for each cycle of operation of the converter. An over-voltage protection circuit for the output of the converter is also provided.

Growing community of inventors

Lewis Center, OH, United States of America

Kenneth Andrew Wallace