Semiconductor Components Industries, LLC

Globalfoundries Inc.

Kenneth Andrew Bates

Jeffrey P Gambino

David T Price

Angel L Rodriguez

Jeffery Allen Neuls

Rick Mauritzson

Sameer S Haddad

Andy C Wei

Guillaume Bouche

Jinping Liu

Huang Liu

Haigou Huang

Weize Chen

Mark Griswold

Xintuo Dai

Huy Cao

Bharat V Krishnan

Bruce Greenwood

Haifeng Sheng

Chang Ho Maeng

Shyam Pal

Anthony Ozzello

Ja-Hyung Han

SangWoo Lim

An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

Process of forming an electronic device including a non-volatile memory cell

Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

Stacked image sensor capacitors and related methods

Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiOlayer; forming a metal layer over the SiOlayer; and planarizing the metal and SiOlayers down to the gate cap layer.

Siloxane and organic-based MOL contact patterning

Growing community of inventors

Happy Valley, OR, United States of America

Kenneth Andrew Bates