Focus Enhancements, Inc.

Tektronix, Inc.

Kenneth Alfred Boehlke

Steven R Morton

A synchronizing signal generator produces a PAL standard horizontal synchronizing signal using a standard subcarrier signal as a timing reference. The synchronizing signal period is not an even multiple of the subcarrier signal period. To produce the synchronizing (sync) signal, the generator first frequency multiplies and divides the input signal to produce a reference signal having a period that is a rational multiple of the subcarrier signal period but smaller than the desired sync signal period. The generator then delays each successive pulse of the reference signal by increasingly longer delay times to produce the sync signal.

Video synchronizing signal generator

A video converter converts an input video signal conveying pixel data representing an M.times.K pixel image to an output video signal conveying data representing an N.times.L pixel image. The converter samples the input video signal to acquire an M.times.K matrix of pixel data, re-encodes each pixel data value as necessary to meet color coding requirements of the output video signal standard, and then employs digital interpolation and/or decimation filters to convert the M.times.K data matrix to an N.times.L data matrix. A simple digital output encoder operating at four times the output video signal subcarrier frequency is then employed to process the N.times.L matrix to produce a digital output data sequence which, when applied to D/A converter, becomes the output video signal.

Video signal converter utilizing a subcarrier-based encoder

A bilinear decimator converts an input data sequence representing a high resolution image formed by N horizontal pixel lines to an output data sequence representing a lower resolution image formed by P horizontal pixel lines where N&gt;P. The decimation ratio P/N can be any rational fraction. When the decimation ratio reduces to the form 1-(1/n), the decimator computes the each output sequence data value as a simple weighted average of pixel data values for two vertically adjacent high resolution image pixels. When the decimation ratio is other than of the form 1-(1/n), the decimator adds additional terms to the computation of output pixel data values when necessary to compensate for aliasing errors.

Bilinear decimator with error compensation

A digital phase shifter produces from an input clock signal quadrature pairs of the input clock signal. The quadrature pairs are mixed and summed in response to a desired phase angle control signal to produce a phase shifted clock signal. The quadrature pairs are produced from a counter having as input a signal at four times the input clock signal frequency, with one output being a signal at the input clock signal frequency. The clock output signal is delayed one-quarter of a cycle to form a quadrature clock output signal, and the in-phase and quadrature clock output signals are converted to complementary quadrature signals. The complementary quadrature signals are input to a double 4:1 multiplexer so as to produce for any selection signal a quadrature pair of signals at the output defining one of four quadrants. The selected quadrature pair is mixed in a 2:1 multiplexer by a selection signal that alternates between states as a function of the comparison between the most significant bits from the counter and a fine angle control signal. The output from the multiplexer is bandpass filtered at the input clock frequency to produce the phase shifted clock signal.

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Beaverton, OR, United States of America

Kenneth Alfred Boehlke