Sun Microsystems, Inc.

Advanced Micro Devices Corporation

Digital Equipment Corporation

Kenneth Alan House

Kamran Zarrineh

Claude R Gauthier

Spencer Montgomery Gold

Joseph Raymond Siegel

Emrys J Williams

Paul C Miranda

Steven R Boyle

John Kirk

Charles K Bachand

Seokjin Kim

Syed A Obaidulla

Lawrence Narhi

An integrated circuit device includes a first plurality of non-volatile memory locations such as fuses that supply programmed values corresponding to initially selected device features such as voltage, frequency, clock speed, and cache parameters. The device is programmed with a lock value in a second plurality of non-volatile memory locations. That lock value may be a randomly generated number that is unique for each device. After initial programming of the device, access to the device is prevented by appropriately programming access control. In order to unlock the device and modify device features, an unlock key value is supplied to the device. If the unlock key value correctly corresponds to the lock value, the device features can be modified. In that way device features can be modified, but security is maintained to prevent unauthorized modification to device features.

Method and apparatus to control access to device enable features

A memory BIST architecture provides an efficient communication interface between external agents, e.g., external tester and a memory BIST module. The memory BIST architecture reduces diagnostics efforts by dividing the search space and allowing the test and debug to be concentrated on the failing memory. The memory BIST architecture is divided into two levels, a memory BIST sequencer level and a satellite memory BIST module. The memory BIST sequencer level includes a set of registers that provide an interface between external agents attempting to communicate with the MBIST module and the Satellite MBIST module.

Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors

A semiconductor device includes at least one component which is vulnerable to damage during scan testing for a particular input data configuration, and supports a safe mode in which this particular input data configuration is disabled. The semiconductor device also includes a port for receiving an input scan vector for scan testing, and an authorization unit connected to said port. The authorization unit maintains the device in safe mode if an input scan vector does not satisfy at least one predetermined criterion. In one particular implementation, the authorization unit generates a digital signature for the input scan vector, which is then compared to a signature portion included within the input scan vector itself. Scan testing is enabled providing that this comparison finds a match.

Semiconductor device and method and apparatus for testing such a device

A method of testing an embedded memory which includes providing a programmable memory built-in self-test module and using the programmable memory built-in self-test module to extract contents of the embedded memory upon detection of an error. The programmable memory built-in self-test module includes a pseudo binary search and stop on error function.

Method and apparatus for at-speed diagnostics of embedded memories

A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

Method and system for monitoring and profiling an integrated circuit die temperature

A controller and method are provided for monitoring and controlling a temperature of an integrated circuit to inhibit damage from a thermal problem. The controller and method allow for individual temperature thresholds for each of one or more temperature sensors. Digital filtering of values received from temperature sensors is also provided. A variety of actions can be selected for execution upon a determination of an over-temperature condition of the integrated circuit, including assert an over-temperature pin, assert an over-temperature bit in an error register of said controller, assert an over-temperature bit in an error register of said microprocessor, issue an over-temperature interrupt to a service bus of said integrated circuit, cause a trap, slow an operating frequency of said integrated circuit, stop said integrated circuit, and do nothing.

Controller for monitoring temperature

A sensor and method are provided for sensing a physical stimulus in an integrated amount, such as thermal energy and produce a signal that indicates a quantitative value of the physical stimulus along with a value that indicates the operability of the sensor and a value that indicates a sense operation is in process. The sensor and method minimize the number of input and output pins necessary for a sensor to report a measurement response of a physical stimulus.

Two-pin thermal sensor calibration interface

Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.

System and method for automatic generation of an at-speed counter

A bus interface employs a bus extender for connecting an auxiliary bus to a single port on a main bus in such a way as to interconnect one or more host computers on the main bus to one or more peripheral devices on the auxiliary bus. The bus extender employs a transceiver coupled to the main bus, another coupled to the auxiliary bus, and signal transfer and logic circuitry passing signals between and controlling the operation of the transceivers. The circuitry also performs all address translation necessary for inter-bus communication. Once communication links have been established with the designated devices on the other bus, the extender sends message data signals received over the one bus directly onto the other bus without modification. Since the interface can comply with SCSI standards, any of a variety of types of commercially available peripheral devices having controllers complying with those standards can be supported on the auxiliary bus.

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Arlington, MA, United States of America

Kenneth Alan House