Raytheon Company

Hughes Aircraft Company

Kenneth Alan Essenwanger

Lloyd Frederick Linder

Don C Devendorf

Erick M Hirata

Reza Tayrani

William W Cheng

Clifford W Meyers

Tomas Lang

Milos D Ercegovac

Sen W Chu

Allen L Sakai

Provided are assemblies and processes for efficiently coupling wideband differential signals between balanced and unbalanced circuits. The assemblies include a broadband balun having an unbalanced transmission line portion, a balanced transmission line portion, and a transition region disposed between the unbalanced and balanced transmission line portions. The unbalanced transmission line portion includes at least one ground and a pair of conductive signal traces, each isolated from ground. The balanced portion does not include an analog ground. The transition region effectively terminates the analog ground, while also smoothly transitioning or otherwise shaping transverse electric field distributions between the balanced and unbalanced portions. Beneficially, the balun is free from resonant features that would otherwise limit operating bandwidth, allowing it to operate over a wide bandwidth of 10:1 or greater. Assemblies can include RF chokes with back-to-back baluns, and other elements, such as balanced filters, and also can be implemented as integrated circuits.

Wideband, differential signal balun for rejecting common mode electromagnetic fields

Provided are assemblies and processes for efficiently coupling wideband differential signals between balanced and unbalanced circuits. The assemblies include a broadband balun having an unbalanced transmission line portion, a balanced transmission line portion, and a transition region disposed between the unbalanced and balanced transmission line portions. The unbalanced transmission line portion includes at least one ground and a pair of conductive signal traces, each isolated from ground. The balanced portion does not include an analog ground. The transition region effectively terminates the analog ground, while also smoothly transitioning or otherwise shaping transverse electric field distributions between the balanced and unbalanced portions. Beneficially, the balun is free from resonant features that would otherwise limit operating bandwidth, allowing it to operate over a wide bandwidth of 10:1 or greater. Assemblies can include RF chokes with back-to-back baluns, and other elements, such as balanced filters, and also be implemented as integrated circuits.

A space-efficient broadband balun (). The balun () includes a first mechanism () for receiving an input signal () having an undesirable component. A second mechanism () rejects the undesirable component via a waveguide transition (). In a specific embodiment, the undesirable component is a common mode component. The first mechanism () includes an input microstrip waveguide (). The waveguide transition () is a single microstrip-to-slotline transition () from the input microstrip waveguide () and to a slotline () in a ground plane () of the microstrip waveguide (). The slotline () is terminated at a first end () via a wedge () in the ground plane (). A second end () of the slotline () provides an output of the balun (). The input signal () includes a first input signal () and a second input signal (), which are input at opposite ends () of the input microstrip waveguide (). The first input signal () and the second input signal () have a desired differential mode component and an undesired common mode component.

Compact balun for rejecting common mode electromagnetic fields

A compact broadband balun (). The balun () includes a waveguide transition () between one or more input ports () and one or more output ports () of the balun (). A mechanism (), which depends on the tapered transition (), provides a good match, while a resistor () provides isolation between input ports () and the output ports (). In a specific embodiment, the balun () includes a first waveguide (). One end of the first waveguide represents a first port of the balun (). The balun () further includes a second wave guide (). Opposite ends () of the second waveguide () represent second () and third () ports. The waveguide transition () occurs between the first waveguide () and the second waveguide (). The waveguide transition () is designed to provide a frequency-independent anti-phase response in response to an input signal provided at an input port (). In alternative embodiment, microstrip waveguides are employed, and port inversion is achieved via a slotline inverter strategically positioned in the groundplane of the balun.

Compact broadband balun

A direct digital synthesizer (DDS) generates a sinusoidal waveform having a variable frequency within a time duration. The DDS has a memory for storing pre-computed digital values defining the sinusoidal waveform, a barrel shifter for reading the contents of the memory and for presenting the digital values from the memory to a multiplexer at a first rate determined by a first clock. The multiplexer is connected to a Digital to Analog converter. The Digital to Analog converter converts the digital values presented by the multiplexer to the analog output at a second rate determined by a second clock. The barrel shifter shifts the digital values using a plurality of pipelines and n-bit wrap-around registers. Pre-computed digital values defining the sinusoidal waveform are stored within a memory, then routed using a bus exchange switch to the barrel shifter.

Multi-bit output DDS with real time delta sigma modulation look up from memory

An Advanced Digital Antenna Module (ADAM) for receiving and exciting electromagnetic signals. The ADAM ASIC integrates a complete receiver/exciter function on a monolithic SiGe device, enabling direct digital-to-RF (Radio Frequency) and RF-to-digital transformations. The invention includes an improved analog-to-digital converter (ADC) ( ) with a novel active offset method for comparators. The novel ADC architecture ( ) includes a first circuit ( ) for receiving an input signal; a second circuit ( ) for setting a predetermined number of thresholds using a predetermined number of preamplifiers ( ) with weighted unit current sources ( ) in each of the preamplifier outputs; and a third circuit ( ) for comparing the input to the thresholds. In the preferred embodiment, the ADC ( ) includes trimmable current sources ( ). The ADC ( ) of the present invention also includes an improved comparator circuit ( ). The novel comparator ( ) includes split load resistors, pairs R (active mode) and R and pairs R (active mode) and R , to increase the acquisition time and reduce the regeneration time constant, emitter follower buffers Q and Q on the latch pair transistors Q and Q to reduce the capacitive loading on the regeneration node, and cascode transistors Q and Q coupled to the load resistors to eliminate the output loading effects from the regeneration node. In the preferred embodiment, the invention also includes a novel DDS/DAC architecture ( ) with digitally trimmed unary currents and a novel sine lookup and decoder design which overcomes the conventional dynamic range limitations at high conversion rates.

Advanced digital antenna module

Digital-phase to digital amplitude translator with first bit off priority coded output for input to unit weighed digital to analog converter

A digital phase to digital sine and cosine amplitude translator generates sine and cosine outputs from an input angle word, which is decomposed into the most significant bits (MSBs) and the least significant bits (LSBs), and the octant number of the angle is identified by the octant identifier bits. Radix-4 multiplier/adder circuits improve the efficiency of multiplication/addition computations. An incrementor and a decrementor are used for sine and cosine MSB computations, respectively, to further save the computer memory and logic. In a preferred embodiment, the MSBs of the sine and cosine outputs for all octants are generated based upon the octant number of the input angle, and the LSBs of the outputs are generated by trigonometric approximations and octant selection, thereby resulting in a savings in computer memory and logic.

Digital phase to digital sine and cosine amplitude translator

A DAC converts a sequence of digital codewords into an approximately piecewise linear analog waveform that follows rising and falling edges between plateau levels. The DAC processes, in parallel, each bit of the codewords to produce component waveforms that are weighted according to their bits significance and summed together to produce the piecewise linear analog waveform. Waveform shaping circuits control the rise and fall times of each component waveform so that the analog waveform's rising and falling edges settle to within a desired error bound of a linear output ramp whose slope is a function of the difference between successive codewords and the rise or fall times. The rise and fall times are preferably approximately the same. Limiting switches control the plateau levels of the component waveforms so that the analog waveform's plateaus settle to within the desired error bound of the ideal values represented by the codewords. The linear region of the limiting switches are expanded to maintain the linearity of the rising and falling edges established by the waveform shaping circuits.

Digital-to-analog converted (DAC) and method that set waveform rise and

A direct digital synthesizer (DDS) accumulator circuit is disclosed wherein a selected few of the low order accumulator bits are dithered by a pseudorandom number generator in order to introduce flat frequency deviation density to suppress spurious signals including those close-in to the output or fundamental frequency. The accumulator circuit may advantageously be sectioned into a lower order accumulator and higher order accumulator in a pipelined combination with a sine approximation output circuit in order to construct a DDS circuit wherein such spur suppression is achieved without decreasing system throughput.

Growing community of inventors

Walnut, CA, United States of America

Kenneth Alan Essenwanger