International Business Machines Corporation

Cray Research, Inc.

Kenneth A Van Goor

James David Strom

David Howard Allen

Grant Paul Kesselring

Helmut Schettler

Mark Ronald Sikkink

Roger John Gravrok

Kennedy K Cheruiyot

Edward F Culican

Philip E Pritzlaff, Jr

David I Sanderson

Arthur H Orth

Gregory R Edlund

A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.

Implementing compact current mode logic (CML) inductor capacitor (LC) voltage controlled oscillator (VCO) for high-speed data communications

A method and circuit for implementing differential resonant clocking with a DC blocking capacitor, and a design structure on which the subject circuit resides are provided. An on-chip inductor and an on-chip capacitor are connected between a pair of differential active clock load nodes to form a resonant tank circuit. The on-chip inductor has a selected value based upon a value of a load capacitor of the differential active clock load nodes to determine the resonant frequency. The on-chip capacitor has a selected value substantially greater than the value of the load capacitor.

Implementing differential resonant clock with DC blocking capacitor

An integrated circuit includes a first clock island, a second clock island, a clock generator, and a first programmable delay element. The first clock island is configured to receive a first clock signal. The second clock island is configured to receive a second clock signal. The clock generator is configured to provide a generated clock signal and the first and second clock signals are based on the generated clock signal. The first programmable delay element is coupled between the clock generator and the first clock island. The first programmable delay element is configured to receive the generated clock signal and provide the first clock signal. The integrated circuit is configured to account for a clock skew between the first and second clock signals when information is transferred between the first and second clock islands. In this manner, a predetermined amount of the clock skew may be introduced between the first and second clock signals to smear out, over time, instantaneous power supply current demands of respective logic within the first and second clock islands.

Power supply current spike reduction techniques for an integrated circuit

The skew of a circuit within a clock pulse distributing network is determined by establishing a closed loop circuit including the circuit under test. A sampling period is established such as by a counter actuated by the clock pulses. During that sampling period, the number of pulses recurring within the closed loop circuit are counted in yet another counter. The count is then useful not only to indicate the magnitude of the circuit skew but also allows optimization of the delay introduced to the circuit under test during normal operation. The skew is thus determined dynamically under typical machine environment situations.

Clock pulse measuring and deskewing system and process

A circuit for enhancing the ability of digital circuits to drive highly capacitive loads is disclosed. The circuit has particular utility when employed with logic circuits such as 'TTL' (Transistor-Transistor Logic) and 'DTL' (Diode-Transistor Logic).

Speed up of up-going transition of TTL or DTL circuits under high

Growing community of inventors

Fall Creek, WI, United States of America

Kenneth A Van Goor