Alliance Semiconductor Corporation

Kenneth A Poteet

Chitranjan N Reddy

Subramani Kengeri

Vipul C Patel

Darryl G Walker

Michael C Stephens, Jr

A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an external address in the set-up time prior to the rising edge of the external clock. A timing and control circuit (18) generates a word line enable (WLE) signal in synchronism with the rising edge of the external clock. When active, WLE activates a word line driver (34), when inactive, WLE equalizes the bit lines. WLE is applied to a first delay circuit (60) to generate a sense signal (SA). SA activates a sense circuit (46) and deactivates the WLE signal. Consecutive pipelined accesses are achieved such that, as an address is decoded, the bit lines are equalizing and the data from the previous address are propagating through a data I/O path (16).

Staggered pipeline access scheme for synchronous random access memory

A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12). The channel width of the inverter NMOS transistors (N2) are relatively large in relation to the inverter PMOS transistors (P2), allowing the NMOS transistors (N2) to be turned on by a voltage of Vcc-Vtn, where Vtn is the threshold voltage of the transfer transistors (N0).

Reduced area word line driving circuit for random access memory

A burst dynamic random access memory (DRAM) (10) is disclosed having memory cells arranged in a number of quadrants (22), each quadrant including local I/O lines (24) for accessing the memory cells therein. The local I/O lines (24) of each quadrant are commonly coupled to global I/O lines (26) by tri-state driver banks (30). According to a row address and a first portion of a column address, a row decoding circuit (36) and column decoding circuit (40) couple one set of local I/O lines (24) within each quadrant (22) to selected columns within the quadrants (22). A bank sequencer (48) receives a second portion of the column address and generates burst sequence of different bank select signals. Each bank select signal enables a different set of tri-state driver banks (30). The enabled tri-state driver banks (30) provide a data path between the local I/O lines (24) and the global I/O lines. By enabling a different combination of tri-state driver banks (30) for each bank select signal, burst access is provided to the burst DRAM (10).

Burst random access memory employing sequenced banks of local tri-state

A timing control circuit (10) is disclosed that provides a timing circuit (12) for controlling the operation of an I/O path circuit (14) in a synchronous static random access memory (SRAM). In a read or write operation, the timing circuit (12) sequentially disables bit line equalization circuits (34), enables sense amplifiers (38), disables I/O line equalization circuits (42), and enables secondary sense amplifiers (44). Further, the timing control (12) initiates a reset operation prior to the completion of the read or write operation. The reset operation includes sequentially enabling the bit line equalization circuits (34), disabling the sense amplifiers (38), enabling the I/O line equalization circuits (42), and disabling the secondary sense amplifiers (44). The timing circuit (12) includes first, second and third delay circuits (20, 22, and 24) to allow for minimum split times for bit line pairs (32) and I/O line pairs (40), and minimum secondary sense amplifier (44) sensing times.

Timing control circuit for synchronous static random access memory

A dual-port semiconductor memory device is disclosed that includes a number of array blocks (12) having memory cells disposed in rows and local columns, with each local column having a local bit line pair (30). A sense amplifier row (28) is associated with each array block (12) and includes a sense amplifier (28) coupled to each local bit line pair (30). Each sense amplifier row (14) is commonly connected through a number of bit line gates (32) to global bit line pairs (26) disposed on a higher fabrication layer than that of the local bit lines (30). A block decode signal commonly activates all the bit line gates (32) of one array block to couple the global bit lines (26) to one sense amplifier row (14). The global bit lines (26) are also connected to a column decoding section (18) which provides random input/output selection of a global bit line pair (26). A latch row (20) is also coupled to the global bit lines ( 26) through a number of latch gates (42). The latch gates (42) provide parallel input/output to the global bit line pairs (26). The latch row (20) is coupled to a serial shift register (22) for serial output of data stored within the latch row (20). In an alternate embodiment, there are one half the number of global bit line pairs (26) as there are local bit line pairs (30) in a given block array (12). Even and odd local bit line pairs (30) are multiplexed onto the global bit lines (26) by pairs of bit line gates (32). Correspondingly, the global bit lines (26) are multiplexed to even and odd latches (40) in the latch row (20).

Dual-port random access memory having reduced architecture

A semiconductor random access memory (RAM) is disclosed having a number of array blocks (14), each array block (14) including standard rows, standard columns, redundant rows (24) and redundant columns (26). A row redundancy circuit (44) is provided for each array block that includes a single row fuse bank (28). Within the row fuse bank (28) are row disable fuses (42) and redundant row fuses (54) interspersed at regular intervals between the row disable fuses (42). Each row disable fuse (42) disables a standard row segment (32) when opened. A redundant row segment (46) is driven according to the combination of opened redundant row fuses (54). A column redundancy circuit (62) includes a number of column fuses (64) disposed in a column fuse bank (30). Redundant columns (26) are enabled by opening selected ones of the column fuses (64). If a redundant column (26) is driven the remaining standard columns of its associated array block (14) are disabled. Column fuse banks (30) are commonly aligned with row fuse banks (28) along fuse axes (16 and 18).

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San Jose, CA, United States of America

Kenneth A Poteet