Texas Instruments Corporation

Kenneth A Poteet

Duy-Loan T Le

Joseph H Neal

Roger D Norwood

Karl M Guttag

Wilbur Christian Vogley

Steven D Krueger

Anthony M Balistreri

Joseph P Hartigan

Scott E Smith

Basavaraj I Pawate

Vipul C Patel

Michael C Stephens, Jr

Jim C Tso

Joe H Neal

Duy Loan Le

Michael V Ho

Duc Ho

A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

High-speed memory arranged for operating synchronously with a

High speed memory arranged for operating synchronously with a

Data processing system arranged for operating synchronously with a high

Random access memory with latency arranged for operating synchronously

A smart memory (10) is provided that includes data storage (12 and 18) and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard memory device. In a first mode of operation, the smart memory (10) is a data storage facility for an associated central processing unit (22). In a second mode of operation, the smart memory (10) is a storage facility for the processing core (14 and 16) and for central processing unit (22) for simultaneous execution of instructions. The central processing unit (22) controls the mode of operation and determines the instructions executed by the processing core (14 and 16). The wide data bus, available with an integrated processor/storage facility, permits certain processing operations to be off-loaded to the smart memory (10) where the processing operations can be performed more efficiently.

Apparatus and method for a memory unit with a processor integrated

Random access memory arranged for operating synchronously with a

An oscillator (108) for a standby charge pump (102,104)in a dynamic random access memory part (30) includes a fuse (136). The fuse can be blown after testing the part while selecting redundant memory cells to reduce the frequency of the oscillator and obtain a lower power part. The oscillator (108) also drives the on-chip self-refresh circuits (106) that operate slower in response to the reduced frequency. Selecting redundant circuits also includes eliminating memory cells that pass the pause test, but by only a certain margin. Reducing the frequency of the oscillator driving the self-refresh circuits would otherwise cause failure of the cells that pass the pause test by only the certain margin. The oscillator circuit includes a ring of inverter stages (112) and a fused voltage bias circuit (110) generating one or another set of bias voltages (118,120) to the ring oscillator to alter its frequency of oscillation.

Process of making and a DRAM standby charge pump with oscillator having

Switching circuits controlled by a fuse that can be blown after testing the DRAM part select the timing signals coupled from a binary counter to internal signal generator circuits. The internal Circuits control self refresh in this embodiment. The decision to leave the fuse intact or blow the fuse rests on the test results obtained from each part and can vary depending upon maturity of the manufacturing process, the pause test results obtained and whether a low power part is desired. The fuse is affected after fabrication of the chip and at the same time as other fuses used for redundancy. This provides another degree of freedom in the manufacture of integrated circuits.

Fuse selectable timing signals for internal signal generators

System including a data processor, a synchronous dram, a peripheral

Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.

Dual receiver edge-triggered digital signal level detection system

A 1M.times.2 parity DRAM is salvaged from a defective 1M.times.4 parity DRAM having two or less unrepairable memory quadrants. Circuits are designed so 'any' combination of 2 good quadrants can be accessed as a result of fuse blowing and steering logic which is controlled by the fuse signals.

Method and apparatus for implementing .times.2 parity DRAM for 16 bit

A semiconductor memory architecture, which includes a given number of discrete components, provides a memory module of increased capacity. The memory module includes a plurality of discrete data memory circuits each organized to provide an individual data string having a length that is an integer multiple of four bits. Each memory circuit has a different separate data lead. A row address strobe signal is applied to the memory circuits. A different column address strobe signal is applied to pairs of the memory circuits. Another discrete memory device includes plural dynamic cell arrays, each of the dynamic cell arrays having a terminal for receiving a row address strobe and a different separate data lead. Each of the dynamic cell arrays has a terminal for receiving a different column address strobe signal.

Memory module arranged for data and parity bits

A semiconductor memory architecture, which includes a given number of discrete components, provides a memory module of increased capacity. The memory module includes a plurality of discrete data memory circuits each organized to provide an individual data string having a length that is an integer multiple of four bits. The data memory circuits are arranged to provide a combined data string having a length equal to the sum of the individual data string lengths. Each data memory circuit includes a signal line connected to control transfer of individual data strings. A different data pin is associated with each bit of the combined data string to transfer a datum for output from the memory module. Each signal line is connected to a control pin to receive an external signal for initiating transfer of one of the individual strings from one of the data memory circuits. The module further includes an additional memory circuit having a plurality of additional signal lines and a plurality of additional data lines. A first of the additional signal lines is wired in common with the signal line of a first one of the data memory circuits. A second of the additional signal lines is wired in common with the signal line of a second one of the data memory circuits. The additional memory circuit is responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from one of the data memory circuits.

The described embodiments of the present invention provide a voltage generation circuit for biasing a particular node to a selected voltage level. A circuit is included for monitoring when the voltage supply to the integrated circuit is well above optimal specifications. When this circuit detects an over-voltage condition, a signal is provided to multiplexing circuitry which causes a higher frequency input signal to be provided to a voltage generating charge pump. Thus, the charge pump capacity is increased. In other embodiments of the present invention other factors may be sensed and the appropriate signal supplied to the charge pump driving circuitry to provide higher biasing levels. For example, current may be sensed at the voltage supply inputs to determine when the circuit is drawing a high level of current.

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Houston, TX, United States of America

Kenneth A Poteet