Texas Instruments Corporation

Kenneth A Lies

Jeffrey R Teza

Stephen P Hamilton

Ashok H Someshwar

Arthur C Hunter

A memory interface system employs a communications protocol to distinguish between command signals, address signals and data signals appearing on the same bus lines. Each memory coupled to the bus lines detects the change between a default state on the bus lines and a command signal. A detector within each memory determines from the received command signal the type of memory operation to be performed and prepares the memory for that operation. These operations may include reading or writing data within specified locations in the memory or reading or writing within the program counter associated with the memory. The detector is only responsive to received command signals when a predetermined state follows the default state.

Memory interface system having combined command, address and data buss

A memory mapped I/O scheme treats each I/O buffer as a memory element which can be addressed, written into or read from. Each I/O buffer has its own memory address decoder which eliminates the need for special select/control lines for each buffer and enables the use of a single address/data bus. Thus redesign and reconfiguration of the I/O buffers is more easily accomplished because it does not require new select/control lines to be laid out when buffer locations are changed.

Modular input/output system

An electronic data processing system such as utilized in battery powered hand held calculators having a two mode clock control for control of power consumption. A power consumption controller enables generation of clock signals in an active cycling state for operating the data processing system in an active mode and enables generation of clock signals in a predefined steady state for operating the data processing system in a low power standby mode. In another embodiment of this invention, the power consumption controller generates a preset signal during the standby mode, this preset signal being applied to certain critical circuits of the data processing system to force each critical circuit output to a designer predefined output logic level during the standby mode. The designer predefined output logic level of each critical circuit is selected to prevent static power loads in the standby mode caused by node self discharge.

Clocked logic low power standby mode

A calculator having constant memory utilizing a low power microcomputer with on-chip memory capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved. Power consumption less than conventional CMOS is obtainable.

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Lubbock, TX, United States of America

Kenneth A Lies