Motorola Corporation

Kenneth A Hansen

Gary A Kurtzman

Enrique Ferrer

Ronald H Chapman

Ralph T Enderby

Rajesh H Zele

Charles R Ruelke

Joseph P Heck

Kevin B Traylor

Walter H Kehler

David J Graham

Richard B Meador

Dane E Blackburn

James D Brake

Andrew J Webster

Bronis Vidugiris

A SONAD (110) control system (100) detects a received signal strength (RSSI) for a radio frequency (RF) signal (102), selects a threshold transfer function (400-404) in response thereto, generates a threshold control signal in response to the transfer function, and utilizes the threshold control signal to select the SONAD threshold value. During operation, the control system (100) decreases the attenuation of background noise levels for weak RF signals.

Speech-operated noise attenuation device (SONAD) control system method

A single-chip transceiver integrated circuit (100) has multiple on-chip circuits that implement receiver functions, transmitter functions, and audio processing functions. The IC (100) has interfaces (220, 240, 252, 270, 260, 245, 288, 290) which are situated among the on-chip circuits, and which couple one on-chip circuit to another. At least some of these on-chip interfaces (220, 240, 245, 252, 270) are configurable to couple an off-chip processing circuit to substitute for a corresponding on-chip circuit. In the preferred embodiment, the single-chip transceiver IC (100) supports radio configurations having off-chip versions of corresponding on-chip circuits for performing receiver front-end functions, synthesizer functions, reference oscillator functions, and audio processing functions.

Configuration single chip receiver integrated circuit architecture

A method for acquiring rapid automatic gain control (AGC) response in a narrow band receiver teaches opening the AGC loop (100), setting the gain control signal (106) amplitude of the AGC amplifier stage (104) to a known value, altering the gain control signal (106) amplitude over time, and monitoring the narrow band receiver for an output signal (112). Upon output signal (112) detection, halting alteration of the gain control signal (106) amplitude, closing the AGC loop (100) and commencing normal operation. A particular facet of this approach suggests detecting the output (112) with a varying gain detector (116,132) after the loop (100) is closed and before normal operations are commenced.

Method for acquiring a rapid automatic gain control (AGC) response in a

An audio amplifier clipping avoidance apparatus (140) identifies signal segments of an audio signal that can have an amplitude peak greater than a particular amplifier clip avoidance threshold (530). A scaling factor is determined for each signal segment based on the particular threshold (540). Signal segments are scaled with corresponding scaling factors to produce a modified audio signal having no signal segments with an amplitude peak greater than the particular threshold (560).

Audio amplifier clipping avoidance method and apparatus

A noise squelch circuit for a radio receiver (100) includes an adaptive filter (204) for shaping frequency characteristics of a demodulator out put (115) according to factors which effects squelch sensitivity. Such factors may include channel spacing of the receiver, received signal strength level, received signal deviation, and SINAD. The adaptive filter (204) comprises a switched capacitor filter, the response of which may be controlled by a control signal (212) according to one or more of such factors.

Noise squelch circuit with adaptive noise shaping

A method and arrangement for electronically bandswitching a radio (100) is described which includes at least a receiver (110, 111), a PLL (120), and a fully synchronized, programmable counter as a frequency divider (140) that is coupled between the receiver and the PLL. This fully synchronized divider (140) provides an output signal (143) at a lower frequency with minimal harmonic energy and improves the sideband noise performance as the divisor increases. When the radio also includes a transmitter (104), stepped attenuators (128, 132) are also included for adjusting the modulation of the PLL (120) when in the transmit mode. The PLL includes at least a reference signal generator (121, 122), a phase detector (124), and a voltage controlled oscillator (127) having an output (129) coupled, via a feedback path, to a second input (131) of the phase detector (124). The fully synchronized, programmable frequency divider includes at least a counter, a data loader, a half-period detector, and a synchronizer which are configured and arranged to provide an output signal (143) having a duty cycle, nearly equal to 50%, which is independent of a divisor and which simplifies the filtering requirements thereafter, thereby providing electronic bandswitching for the radio while exhibiting fast-locking and low-noise characteristics.

Two-way radio having a PLL

A method and arrangement for a fully synchronized, programmable frequency divider is disclosed that exhibits a near 50% duty cycle output signal independent of the divisor, whether even or odd, and that is suitable for use in a phase-locked loop (PLL) frequency synthesizer. As described in a first embodiment, the arrangement includes a data loader 31, a counter 32, a half-period detector 33, and a synchronizer 34. Next, a fast-locking, low-noise PLL frequency synthesizer is disclosed incorporating the fully synchronized, 50% duty cycle divider, and having a reference signal generator 71-72, a phase detector 73, a controlled oscillator 74-75, and the fully synchronized, programmable frequency divider 76. In a second embodiment, a fully synchronized programmable divider is described, including a data loader 31, a counter 32, a half-period detector 33', a synchronizer 34', and an additional block 82, a half-clock period detector. Synchronizer 34' is modified to include an additional block 84, an output logic circuit, which allows for an output signal duty cycle virtually equal to 50% for odd as well as even integer divisors.

Fully synchronized programmable counter with a near 50% duty cycle

A programmable frequency synthesizer is disclosed having most components implemented on a single large scale integration (LSI) chip, which facilitates rapid frequency acquisition. Provision is made by the present invention to configure the frequency synthesizer for use in either a receiver or a transmitter. In the transmitter mode, modulation cancelling allows modulation down to approximate DC. A serial programming protocol is provided to program the frequency synthesizer.

Frequency synthesizer

A buffer is described which includes two gain stages which may be constructed of MOS devices, the first stage having a low noise characteristic and the second stage having a high current drive capability. The second stage is switched in circuit only when high current drive is needed so that the buffer otherwise exhibits the low noise characteristics of the first stage. A feedback network is also switched in circuit in a manner that maintains the buffer's loop gain substantially constant, whether or not the high current drive stage is in circuit.

Multiplexed buffer

A low frequency oscillator of the astable type having good frequency stability, fast starting, good immunity to DC loading, and suitable for fabrication in integrated circuit form. First and second switching transistors of the astable multivibrator are cross-coupled by a coupling capacitor and a frequency determining crystal. Base drive to the respective switching transistors and charging current to the capacitor and crystal are provided by a pair of differential amplifiers which are referenced to a forward biased diode. The differential amplifiers are also connected to respective collector terminals of the switching transistors. The capacitor is of small value suitable for containment within an integrated circuit with the oscillator circuit. The differential amplifiers substantially increase the impedance levels in the oscillator and shift base drive to the switching transistors to minimize the effects of DC loading at the output terminals of the oscillator.

Low frequency astable oscillator having switchable current sources

A wide frequency range current-controlled oscillator (CCO) provides a digital output signal that is frequency controllable by an input control current. The CCO includes a differential voltage comparator coupled to a timing capacitor for controlling charging and discharging currents applied to the timing capacitor. The charging and discharging currents are dependent on the input control current. The magnitude of the discharging current may be varied to control the duty cycle of the digital output signal.

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Round Rock, TX, United States of America

Kenneth A Hansen