International Business Machines Corporation

Globalfoundries Inc.

Kenneth A Bandy

Richard Stephan Wise

Yun-Yu Wang

Ahmad D Katnani

Sadanand Vinayak Deshpande

Gary L Milo

Matthew C Nicholls

Scott D Allen

Jeffrey J Brown

Michael Joseph MacDonald

Mark D Levy

Yutong Wu

Jochonia N Nxumalo

Timothy C Milmore

Vincent J Carlos

Stuart D Cheney

Dimitrios Ioannou

Sara L Lucas

Jason Nowakowski

Methods of improving hot carrier parameters in a field-effect transistor by hydrogen reduction. A gate structure of the field-effect transistor is formed on a substrate, and the substrate is heated inside a deposition chamber to a given process temperature for a given time period. After the time period concludes, a conformal layer is deposited at the given process temperature over the gate structure, and is subsequently etched to form sidewall spacers on the gate structure. After the sidewall spacers are formed, a capping layer is conformally deposited over the gate structure and the sidewall spacers, and cured with an ultraviolet light treatment. An interconnect structure may be formed over the field-effect transistor and the capping layer, and a moisture barrier layer may be formed over the interconnect structure. The moisture barrier layer is composed of a material that is permeable to hydrogen and impermeable to water molecules.

Mitigation of hot carrier damage in field-effect transistors

The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device.

Etch process for improving yield of dielectric contacts on nickel silicides

A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.

Multi-run selective pattern and etch wafer process

The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer is deposited on the raised and recessed regions of the semiconductor substrate A selectively removable filler layer is then deposited on the FET protection layer with a thickness to over-fill the recessed regions of the gates of the FETs. The selectively removable filler layer is then planarized until the FET protection layer on top of the gates is exposed. The recessed regions between the gates are left substantially filled with selectively removable filler layer The selectively removable filler layer in the region where the BJT is formed is patterned and an opening is made to allow for the depositing of layers of different materials used in the construction of the BJT. The layer of different materials are processed by methods known in the art to form polysilicon emitter of the BJT. Due to selectively removable filler layer creating a substantially planar surface in the recessed regions of the FETs, little to none of the layers of different materials that are used in the construction of the BJT are deposited within the recessed regions Thus, removal of the layers of different materials ( &prime;), from the FET region is simplified. After removal of the layers of different materials ( &prime;), from the FET region, the selectively removable filler layer is removed selectively to the FET protection layer The FET protection layer is then removed. The recessed regions between the gates of the FETs are free from residual films.

Selectively removable filler layer for BiCMOS process

Growing community of inventors

Milton, VT, United States of America

Kenneth A Bandy