Hitachi, Ltd.

Kokusai Electric Co., Ltd.

Kenjiro Yasunari

Ichiro Imaizumi

Kouya Hoshina

Toshio Tanaka

Yasunobu Kosa

Nobuo Shibasaki

Yoshiharu Nagayama

Senji Shoji

There is disclosed a correlation circuit for spread spectrum communication which reduces the number of constituting elements to attain low power consumption and which can obtain correlation in a short time, to solve a problem that a conventional sliding correlator requires much time to obtain the correlation and that a matched filter increases the power consumption. In the spread spectrum communication correlation circuit, an A/D converter converts a received spread spectrum signal to a digital signal. Under control of a controller, one symbol of signals are written to an S/H circuit with a 16 MHz. clock, shifted for each sample and read to a high-speed correlator from the S/H circuit with a high-speed clock of 1.6 GHz a plurality of times, and the high-speed correlator performs a product sum operation with a spread code with the 1.6 GHz clock. At the same time the reading is performed, the next symbol of signals are written to the S/H circuit.

Correlation circuit for spread spectrum communication

In a conventional correlation circuit for spread spectrum communication, when a sliding correlator is used, much time is required. When a matched filter is used, a problem is that a circuit scale and power consumption are increased. In the present invention, however, there is provided a correlation circuit for spread spectrum communication which minimizes the number of constituting elements, and can reduce the power consumption. In the correlation circuit for spread spectrum communication of the present invention, a spread spectrum received signal is A/D converted and accumulated in a data memory unit by a symbol unit, data rate is converted, and a high-rate MF performs a product sum operation processing at a high rate so that a correlation output is obtained.

Correlation circuit for spread spectrum communication, demodulation circuit and reception apparatus

A microprocessor having a plurality of memories comprises an address selection means which supplies selectively, to the memories, the address signal generated by the address generation means provided in the microprocessor and the test address signal supplied from the external circuit. Thereby, the address of memories can be accessed directly from the external circuit for the test of memories. Moreover, the microprocessor is provided with the test bus through which the signal transmitted between the function blocks in the microprocessor is input or output from or to the external circuit. Accordingly, the function block can be tested easily.

Semiconductor integrated circuit device

This invention relates to a method of producing a semiconductor device, and more particularly to a method of leading out an electrode for a semiconductor substrate. A conductor layer of polycrystalline silicon or the like is formed on the surface of the semiconductor substrate on which the substrate electrode is to be formed, a desired semiconductor region having a conductivity type opposite to that of the substrate is selectively formed under this state, and the semiconductor substrate electrode is formed on the substrate surface after removing the conductor layer.

Method of producing a semiconductor device

In a semiconductor integrated circuit device in which a plurality of regions each having a semiconductor element such as a PN junction diode and a transistor are isolated electrically from one another by PN junctions formed between the respective regions and a semiconductor isolation region, gold is introduced into the regions having the semiconductor elements and the isolation region while at least one diffused region heavily doped, for example, with phosphorus is formed in the isolation region adjacent to the region having the PN junction diode or the transistor thereby to prevent the breakdown voltage of the backwardly biased PN junction in the diode or the transistor from decreasing. Further by surrounding all the transistors, at least in one of which gold is diffused, formed in one integrated circuit with heavily doped N.sup.+-type regions an integrated circuit with transistors having a small variation in current amplification factor is obtained.

Growing community of inventors

Tokyo, Japan

Kenjiro Yasunari