Kabushiki Kaisha Toshiba

Kenjiro Kanayama

Tadashi Yabuta

Osamu Matsumoto

Hidekazu Saito

Seiji Hinata

Tsukasa Miyawaki

Naoki Taniguchi

Toshiyuki Shinoda

Eishirou Take

An oscillation circuit stops the oscillation of an external oscillator to reduce the current consumed when a frequency lower than the inherent frequency of the external oscillator is supplied to a microcomputer. A PLL circuit 37 generates a second clock 45 from a first clock 23 output by an oscillation circuit 1. A PLL lock signal 47 is changed from a first level to a second level when the second clock 45 is generated. A selector 39 outputs the second clock 45 as an internal clock 13 when the PLL lock signal 47 is at the second level. The operation of an oscillator 9 is stopped when the PLL lock signal 47 is at the second level.

Clock generator in which external oscillator is disabled after internal

A spare decoder has a first register, a second register, and a multiplexer for selecting the output of the first register or that of the second register. The first register stores data of a fuse element. In the ordinary operating mode, a defective memory cell is replaced by a spare cell in accordance with the data stored in the first register. In the test mode, it is determined whether at least one spare cell is defective or not. If there are no defective spare cells, the data that should be stored in the defective memory cell is written into one of the spare cells. Further, the address of the defective memory cell is written into the second register. The defective memory cell is replaced by one of the spare cells in accordance with the data stored in the second register, by cutting the fuse element in accordance with the address of the defective memory cell.

Semiconductor memory device having both redundancy and test capability

An arithmetic operation processing unit provided with an external program memory storing a high speed instruction group for executing a specific routine of arithmetic operations which require high speed execution is shown. The arithmetic operation processing unit comprises a start address register for holding a starting address of the specific routine of arithmetic operations and an end address register for holding an end address of the specific routine of arithmetic operations, an FIFO type RAM for storing microcodes obtained by decoding the high speed instruction group. The high speed instruction group stored in the program memory is sequentially read out by a first instruction execution control means from the start address to the end address and decoded into corresponding microcodes when a high speed instruction group decoding instruction is executed. The microcodes thus obtained are then stored in the FIFO type RAM. The microcodes thus stored in the FIFO type RAM are executed one for each clock when a high speed instruction group execution instruction is executed.

Central processing unit and an arithmetic operation processing unit

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Yokohama, Japan

Kenjiro Kanayama