Renesas Electronics Corporation

Renesas Technology Corp.

Kenji Yoshinaga

Fukashi Morishita

Mihoko Akiyama

Naoya Watanabe

Futoshi Igaue

Katsumi Dosaka

Isamu Hayashi

Teruhiko Amano

Masashi Matsumura

Masakazu Ishibashi

Shinya Miyazaki

A technique is provided that reduces the number of used entries in a CAM required to store a rule. A data conversion device generates entry data which is to be compared with a search key and is stored in an associative memory that can hold three or more values. The data conversion device includes a conversion circuit for extracting a plurality of character strings from an inputted rule in accordance with a regular expression based on the regular expression and converting first and second character strings included in the character strings, respectively, into first and second bit data different from each other, and an encode circuit that compares the first bit data and the second bit data for each bit and generates entry data where each mismatch bit among a plurality of bits included in the first bit data is converted into 'Don't Care' value based on a comparison result.

Data conversion device, search system, and method

The present invention makes it possible to form a circuit configuration that is capable of executing a keyword search at an increased speed while suppressing an increase in the memory capacity of a content-addressable memory. A semiconductor device according to an aspect of the present invention searches an input data string for a predesignated keyword, and includes a first content-addressable memory that stores a partial keyword corresponding to a predetermined number of data beginning with the first data of the keyword, a second content-addressable memory that stores the entirety of the keyword, and a control circuit that is coupled to the first content-addressable memory and to the second content-addressable memory. When a portion matching the partial keyword is detected in the input data string by a search in the first content-addressable memory, the second content-addressable memory executes a search on search data extracted from the input data string.

Semiconductor device and information processing system

An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Content addressable memory with reduced power consumption and increased search operation speed

Content addressable memory

A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Semiconductor device including internal voltage generation circuit

There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.

Semiconductor device

A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.

Growing community of inventors

Itami, Japan

Kenji Yoshinaga