Kabushiki Kaisha Toshiba

Fujitsu Corporation

Mitsubishi Chemical Industries Limited

Konishiroku Photo Industry Co., Ltd.

Fujitsu Hitachi Plasma Display Limited

Liquid Design Systems Inc.

System Fabrication Technologies, Inc.

Kenji Yoshida

Hisashi Kaneko

Koji Miyamoto

Takeshi Fujimaki

Daisuke Miura

Shuji Yoshida

Masayuki Okamoto

Mitsuaki Nagasaka

Toshio Arakawa

Hiroyuki Honda

Kazuyuki Higashi

Junichi Wada

Noriaki Matsunaga

Kazumasa Watanabe

Noboru Mizukura

Takeshi Nishioka

Masaaki Hatano

Ryuichiro Kobayashi

Motoya Okazaki

Yuzuru Sato

Naoshi Kunieda

Makoto Nakazawa

Seiki Kurogi

Hiroshi Nakazawa

Tadanori Oya

Masataka Tsuda

Soichi Inoue

Tadayoshi Kosaka

Masayuki Shibata

Hiroyuki Nakahara

Taichiro Shigematsu

Takashi Katayama

Yoshihiko Koike

Toyohiko Shike

Tetsuya Yoshida

Masayuki Tomida

Hiroshi Kasugai

Yoshitaka Ukai

Yojiro Shimada

Akira Matukuma

Toru Teraoka

Junichi Onodera

Heitaro Obara

Takeo Masuda

A pattern management method includes extracting patterns having process margins equal to or below a predetermined value from a chip layout of an integrated circuit, screening a plurality of types of representative patterns from the extracted pattern, extracting patterns closest to the most outer periphery of the chip from the representative patterns, and representatively managing the extracted patterns which is closest to the most outer periphery of the chip.

Pattern management method and pattern management program

A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program

The present invention provides a semiconductor device which can realize the mounting of a plurality of chips at a high-speed, with high packaging density and at a low cost. In mounting a memory device chipand an ASICon a wiring chip, connection padsare respectively formed along one opposing sides of the memory device chipand the ASICon the wiring chip, the arrangement positions of the respective connection padsdefine the shortest distance assumes the shortest distance therebetween and, at the same time wiring lines which are formed on the wiring chipare also shortened. Accordingly, it is possible to mount the memory device chipand the ASICon the wiring chipwith high packaging density and, at the same time, since the wiring distance can be shortened, the high speed operation can be realized.

Semiconductor device

Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program product

Semiconductor elements composing a semiconductor device are formed on a semiconductor substrate. Wirings composed of copper or an alloy mainly composed of copper are formed in wiring layers through interlayer insulation films to connect the semiconductor elements to each other. When the wirings are formed, a temperature of the wirings is held in a first temperature zone covering &#xb1;40&#xb0; C. of a temperature at which a stress migration is most accelerated.

Method of accelerating test of semiconductor device

By including a unit for storing data to be determined, a unit for delaying the data, a unit for storing the output of the delay unit, and a unit for comparing the storage contents of the data before the delay with the storage contents of the data after the delay, and outputting a marginless status detection signal when they are different, the presence/absence of a margin is monitored regardless of ambient conditions by using an output marginless status detection signal as a switch control signal for a clock switch circuit, thereby operating electronic equipment without changing a frequency of a clock signal up to the critical condition.

Marginless status determination circuit

A plasma display panel is provided in which an operational quality is prevented from being deteriorated by resonance of a substrate. The plasma display panel includes a partition for dividing a discharge gas space defined by a pair of substrates and a sealing material in accordance with a cell arrangement of a display screen. There is a void space between the upper surface of the end portion of the partition and the surface of the opposed substrate, the surfaces contacting each other. The natural frequency of the portion from the inner edge of the void space to the inner edge of the sealing material is raised above audio frequency region of a human.

Plasma display panel

In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.

LSI layout method and apparatus for cell arrangement in which timing is prioritized

Each binary carry logic circuit of half adder circuits other than that for the least significant digit comprises a transfer gate turned on when an input bit A is active and receiving a carry-in bit *C at its data input, and a transistor , turned on when the input bit A is inactive, connected between a power supply potential VDD and the data output of the transfer gate a signal on which is a carry-out bit *C . Transfer gates to of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A to A , letting the carry-in bit *C from the least significant digit propagate through the transfer gate chain at a high speed.

Logic circuit for fast carry/borrow

One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.

Semiconductor integrated circuit device having multilevel interconnection

Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S ) sorting the terminals according to the width thereof; and (S S ) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal. In another embodiment, the method comprises the steps of (a) sorting the terminals, connected to a power supply wire, according to the value of electric current passing through the terminals; and (b) selecting a terminal from the terminals in descending order of the value of electric current and connecting between the selected terminal and an inter-block wire belonging to a same net as the selected terminal.

Method and apparatus for automatic wiring design between block circuits of integrated circuit

A plasma display panel with high accuracy of addressing is provided by suppressing spread of address discharge in the column direction. The plasma display panel includes first main electrodes and second main electrodes for row selection and address electrodes for column selection. A discharge space is continuous over the full length of the screen in each column. The address electrode is patterned in such a way that each first area opposed to the second main electrode is smaller than each second area opposed to the metal film of the first main electrode, in corresponding third areas between partitions of each column of the display panel.

Plasma display panel and method for driving the panel

A plasma display panel includes a plurality of row electrodes defining rows of a screen. The row electrodes are arranged at intervals so that adjacent row electrodes are capable of serving as an electrode pair for generating a surface discharge. Each of the row electrodes includes a belt-shaped base extending along the full length of the screen in a direction of the rows and protrusions extending from the base toward an adjacent row electrode in every column.

Plasma display panel with various electrode projection configurations

Growing community of inventors

Kawasaki, Japan

Kenji Yoshida