Kabushiki Kaisha Toshiba

Other

Toshiba Memory Corporation

Skhynix Inc.

Kenji Tsuchida

Tsuneo Inaba

Haruki Toda

Yukihito Oowaki

Daisaburo Takashima

Hitoshi Kuyama

Yoshihisa Iwata

Yoshihiro Ueda

Shinichiro Shiratake

Masaharu Wada

Hironobu Akita

Yong Ho Kim

Naoki Shimizu

Sumio Ikegawa

Yuui Shimizu

Yohji Watanabe

Ryousuke Takizawa

Toshimi Ikeda

Ji Hyae Bae

Yutaka Shirai

Yoji Watanabe

Hiroaki Yoda

Atsushi Takeuchi

Naoharu Shimomura

Kuninori Kawabata

Katsuhiko Hoya

Hironori Banba

Katsuyuki Fujita

Tomoki Higashi

Kiyotaro Itagaki

Fumihiro Kohno

Yoshiaki Fukuzumi

Takashi Maeda

Takashi Ohsawa

Tatsuya Kishi

Masahiko Nakayama

Junichi Miyamoto

Satoshi Eto

Katsuaki Isobe

Yoshio Okada

Hisanori Aikawa

Kazunori Ohuchi

Takafumi Shimizu

Hiromi Noro

Masako Ohta

Junichi Okamura

According to one embodiment, a semiconductor memory device includes a memory cell, a read circuit, a correcting circuit and a write circuit. The read circuit is configured to read first data from the memory cell by receiving a first command. The correcting circuit is configured to generate second data by correcting an error included in the first data. The write circuit is configured to write the second data to the memory cell in response to receiving a second command.

Semiconductor memory device including a correcting circuit

According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data '0' and data '1' in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittancemiddleat a level inbetween an admittance of a variable resistance element storing data &#x201c;0&#x201d; and an admittance of a variable resistance element storing data &#x201c;1&#x201d;, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.

Semiconductor memory device with variable resistance element

A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.

Nonvolatile random access memory including control circuit configured to receive commands at high and low edges of one clock cycle

A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage.

Semiconductor storage device comprising magnetic tunnel junction elements and write amplifiers

According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Nonvolatile random access memory

According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio &#x2267;|I/I|&#x2212;1 is satisfied if a critical current of the first direction used to write the magnetoresistive element to the parallel state is set to Iand a critical current of a second direction used to write the magnetoresistive element to the anti-parallel state is set to I.

Magnetic memory

Semiconductor storage device

According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data '0' and data '1' in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle between an admittance of a variable resistance element storing data &#x201c;0&#x201d; and an admittance of a variable resistance element storing data &#x201c;1&#x201d;, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.

According to one embodiment, a magnetic memory includes a magnetoresistive effect element including a first magnetic layer invariable in magnetization direction, a second magnetic layer variable in magnetization direction, and an intermediate layer between the first magnetic layer and the second magnetic layer, an error detecting and correcting circuit which detects whether first data in the magnetoresistive effect element includes any error and which outputs error-corrected second data when the first data includes an error, a writing circuit which generates one of the first write current including a first pulse width and the second write current including a second pulse width greater than the first pulse width, and a control circuit which controls the writing circuit to pass the second write current through the magnetoresistive effect element when the second data is written into the magnetoresistive effect element.

A resistance change memory of an aspect of the present invention including memory cells including resistance change memory element, word lines connected to the memory cells, a row decoder which activates the word lines, redundant cells used instead of defective cells, a redundant word line connected to redundant cells, a redundant row decoder which activates the redundant word line, a control circuit in which defect address information indicating the word line connected to the defective cell is stored and which remedies the defective cell, and regions provided in a memory cell array and a redundant cell array and identified based on column address information, wherein the control circuit replaces a part of the word line connected to the defective cell with a part of the redundant word line in accordance with each of the regions, and allows the redundant row decoder to activate the replaced redundant word line.

Resistance change memory

A resistance change memory device includes memory cells including two transistors connected in parallel between a first node and a connecting node and a variable resistance element whose one end is connected to the connecting node. The first node of each memory cell and a second node, which is the other end of the variable resistance element of the memory cell, are connected to different bit lines. The first node of a one memory cell and the first node of another memory cell which is adjacent on a first side along the second axis to the one memory are connected to the same bit line. The second node of the one memory cell and the second node of still another memory cell which is adjacent on a second side along the second axis to the one memory cell are connected to the same bit line.

Resistance change memory device

A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.

A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of a rising edge to the end of the rising edge, and flowing the write current through the magnetoresistive effect element which comprises a first magnetic layer having an invariable magnetizing direction, a second magnetic layer having a variable magnetizing direction, and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer, to change the magnetizing direction of the second magnetic layer.

Data writing method for magnetoresistive effect element and magnetic memory

A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier.

Resistive memory

Growing community of inventors

Kawasaki, Japan

Kenji Tsuchida