Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electric Co., Ltd.

Kenji Toyoda

Takashi Ohtsuka

Kiyoyuki Morita

Takeshi Takagi

Michihito Ueda

Koichiro Yuki

Kiyoshi Morimoto

Yoshihiko Kanzawa

Minoru Kubo

Teruhito Ohnishi

Toru Iwata

Takashi Nishikawa

Jun Kajiwara

In a sensing element for a nitrogen oxide molecule of the present invention, a sensing portion that is to be bonded to a nitrogen oxide molecule to be sensed is fixed between paired metal electrodes through connecting portions. The sensing portion is a single porphyrin molecule or a single porphyrin derivative molecule each having, as a central metal thereof, iron or cobalt. The connecting portions are each a mercaptophenyleneethynyl group bonded to the single porphyrin molecule or the single porphyrin derivative molecule. Provided are a sensing element for nitrogen oxide molecule, a sensing apparatus for nitrogen oxide molecule, and a method for sensing nitrogen oxide molecule.

Sensing element for nitrogen oxide molecule sensing apparatus for nitrogen oxide molecule and method for sensing nitrogen oxide molecule

An organic FET in which the interfaces (electrode interfaces) between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode are improved by employing a technique to increase ON-state current (driving current) and to reduce contact resistance. The organic FET includes a substrate; a gate insulating film disposed on the substrate; a metal source electrode and a metal drain electrode disposed on the gate insulating film in such a manner that they face each other in a horizontal direction; and an organic semiconductor layer covering the gate insulating film, the source electrode and the drain electrode, wherein a first organic molecule layer and a second organic molecule layer are formed on the interfaces (electrode interfaces) between a semiconductor layer and a source electrode and between a semiconductor layer and a drain electrode.

Organic FET having improved electrode interfaces and a fabrication method therefor

The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layerincluding an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

Heterojunction bipolar transistor having reduced driving voltage requirements

A voltage generating circuit comprising a capacitor (), a ferroelectric capacitor () serially connected to the capacitor (), an output terminal (), a capacitor () which grounds the output terminal (), a supply voltage supplying terminal (), a switch () which connects the supply voltage supplying terminal () and the connecting node (N) of the two capacitors (), and a switch () which connects the connecting node (N) and output terminal (); wherein during a first period, with the two switches () and () placed in the OFF state, a terminal () is grounded and a terminal () is provided with a supply voltage; wherein during a second period, the terminal () is provided with the supply voltage and the switch () is placed in the ON state; wherein during a third period, the switch () is placed in the OFF state, the switch () is placed in the ON state, and the terminal () is grounded; wherein during a fourth period, the terminal () is provided with the supply voltage; and wherein thereafter the first through fourth periods are repeated.

Voltage generating circuit, voltage generating device and semiconductor device using the same, and driving method thereof

The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor () when the data signal D is input while a first clocked inverter (), a second clocked inverter (), and a third switching element () are turned on and a first switching element (), a second switching element (), and a third clocked inverter () are turned off; and a data output step of outputting an output signal Q (&#x2212;Q) based on the held data signal D placing the first clocked inverter (), the second clocked inverter (), and the third switching element () in the OFF state and placing the first switching element (), the second switching element (), and the third clocked inverter () in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectric gate transistor ().

Nonvolatile flip-flop circuit and method of driving the same

A non-volatile memory cell comprising a latch circuit () which comprises a first node () and a second node () and latches complementary data set in the first node () and the second node (), a first switching element () which connects the first node () and a first data input/output line (), a second switching element () which connects the second node () and a second data input/output line (), a first ferroelectric capacitor () which connects the second data input/output line () and the first node (), and a second ferroelectric capacitor () which connects the first data input/output line () and the second node ().

Non-volatile memory cell and a method of controlling the same

A ferroelectric gate device which comprises a ferroelectric capacitor (), a switching element () serving as a resistor or a capacitor depending on the voltage applied, and a field-effect transistor () having a source, a drain and a gate, said ferroelectric capacitor () having an input terminal (IN) at one end, the other end of said ferroelectric capacitor () being connected to one end of said switching element (), the other end of said switching element () being connected to the gate of said field-effect transistor (), by applying a voltage to said input terminal, said switching element () serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor () comprises is applied to said ferroelectric capacitor (), and by applying a voltage to said input terminal, said switching element () serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor ().

Ferroelectric element and a ferroelectric gate device using the same

In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistoris connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistoris the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.

Semiconductor device

A method of driving a non-volatile flip-flop circuit comprising a first inverter (INV) coupled to a first memory node () and a second memory node (), a second inverter (INV) coupled to the second memory node () and the first memory node (), a first pass transistor (), a second pass transistor (), a first switching element for control () and a first variable resistor element () which are connected serially to each other and are connected between the first memory node () and a plate line (), and a second switching element for control () and a second variable resistor element () which are connected serially to each other and are connected between the second memory node () and the plate line (), wherein the resistance values of the first and second variable resistor elements () can be changed by the heat generated by a current.

Method of driving a non-volatile flip-flop circuit using variable resistor elements

A ferroelectric gate device which comprises a ferroelectric capacitor (), a switching element () serving as a resistor of a capacitor depending on the voltage applied, and a field-effect transistor () having a source, a drain and a gate, said ferroelectric capacitor () having an input terminal (IN) at one end, the other end of said ferroelectric capacitor () being connected to one end of said switching element (), the other end of said switching element () being connected to the gate of said field-effect transistor (), by applying a voltage to said input terminal, said switching element () serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (), and by applying a voltage to said input terminal, said switching element () serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor ().

A non-volatile memory circuit comprising first and second transistors () each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains of these transistors are connected to each other, whereby a first inverter is formed; third and fourth transistors () each having a gate and a drain, wherein the gates of these transistors are connected to each other and the drains of these transistors are connected to each other, whereby a second inverter is formed; a fifth transistor () provided with a gate, which is connected to a word line (), and which is connected between a first bit line () and an input terminal of the second inverter; a sixth transistor () provided with a gate, which is connected to the word line (), and which is connected between a second bit line () and an input terminal of the first inverter; and first and second resistor elements () which are serially connected to the first and second inverters, respectively, wherein the input terminal and an output terminal of the first inverter are connected to an output terminal and the input terminal of the second inverter, respectively, and the resistance values of the first and second resistor elements (), which are connected to a ground line (), are electrically variable.

Non-volatile memory circuit, a method for driving the same, and a semiconductor device using the memory circuit

Non-volatile latch circuitof the present invention comprises ferroelectric capacitorprovided with a first electrode, second electrode, and ferroelectric filmthat lies between these electrodes; reset terminal Tre that is connected to first electrodeand a CMOS inverter elementthat is connected to second electrodeof ferroelectric capacitor; voltage switching terminal Tpl that applies a voltage to second electrode; switching elementthat is connected between second electrodeand second input terminal Tpl and switches a voltage applied to second electrode; and set terminal Tse that applies a voltage for switching on or off switching element, wherein the voltage generated in second electrodecaused by polarization retained by ferroelectric filmis higher than the threshold voltage Vtn of NMISFETof CMOS inverter element

Non-volatile latch circuit and a driving method thereof

A learning method of a semiconductor device of the present invention comprises a neuro device having a multiplier as a synapse in which a weight varies according to an input weight voltage, and functioning as a neural network system that processes analog data, comprising a step A of inputting predetermined input data to the neuro device and calculating an error between a target value of an output of the neuro device with respect to the input data and an actual output, a step B of calculating variation amount in the error by varying a weight of the multiplier thereafter, and a step C of varying the weight of the multiplier based on the variation amount in the error, wherein in the steps B and C, after inputting a reset voltage for setting the weight to a substantially constant value to the multiplier as the weight voltage, the weight is varied by inputting the weight voltage corresponding to the weight to be varied.

Semiconductor device and learning method thereof

A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

Growing community of inventors

Osaka, Japan

Kenji Toyoda