Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Engineering Company, Limited

Kenji Tokami

Yoshinori Inoue

Yoichi Tobita

Youichi Tobita

Mikio Asakura

Yutaka Ikeda

Takayuki Miyamoto

Takeshi Kajimoto

Takahiro Komatsu

Satoshi Kawasaki

Mikio Sakurai

Tetsushi Hoshita

Kazuhiro Sakemi

An MOS capacitor is provided in the proximity of the boundary between a P well and an N well formed of a bottom N well and an N well. Accordingly, the proximity of the boundary corresponding to the so-called dead space can be used effectively.

Semiconductor device with well of different conductivity types

In this semiconductor integrated circuit device, an internal power supply circuit and an external terminal are connected to each other via a switch circuit having an n channel MOS transistor and a p channel MOS transistor connected in series. While a control signal is input to a gate of the n channel MOS transistor constituting the switch circuit, a control signal inverted by an inverter is input to a gate of the p channel MOS transistor. Thus, both transistors are simultaneously turned on/off by those control signals. When an output voltage of the internal power supply circuit is monitored from the external terminal or when an internal circuit of a semiconductor integrated circuit is driven by a voltage applied to the external terminal, even if a potential of the external terminal overshoots to positive or negative values, the transmission of the potential to the internal circuit is cut off by the n channel MOS transistor or p channel MOS transistor. Therefore, in testing of monitoring of an operating state of the semiconductor integrated circuit and testing of an operating margin for an internal power supply voltage, no adverse influence is exerted on the internal circuit.

Semiconductor integrated circuit enabling external monitor and control

In a semiconductor memory device including a boosting circuit for generating a high voltage constantly, and a word line driving circuit for transmitting a high voltage from the boosting circuit on a selected word line, a capacitor for stabilizing the high voltage generated by the boosting circuit is formed of a series of capacitive elements using a FET having a gate insulating film identical in thickness to that of a insulating gate type field effect transistor in the memory device. A voltage applied across each capacitive element is relaxed, and the capacitor is improved in dielectric breakdown voltage characteristics, to stably supply the high voltage.

Semiconductor memory device including stabilizing capacitive elements

A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.

Semiconductor device including signal generating circuit with level

Semiconductor memory device including a component having improved

In a DRAM, buffer circuits constituting a column address buffer are provided near address input pads receiving external address signals to be input thereto, and switch circuits arranged near the address input pads are connected between the address input pads and a row address buffer. Driving capability of each buffer circuits is set larger than in the prior art. Each switch circuit is controlled to be OFF while a column address signal is being supplied to a corresponding one of the address input pads. While the column address signal is externally applied to the address input pads, the capacitance and resistance of the interconnection layer which affects the waveform of the internal column address signal can be reduced, and hence time required for selecting one column of memory cells in each of memory cell array blocks in response to the external column address signal can be reduced, thus reducing the access time in the DRAM.

Semiconductor memory device and operating method thereof

The present invention is directed to a pulse generating circuit for use in a semiconductor device, in which P type MOS transistors are connected in parallel, series connected N type MOS transistors are connected in series to the P type MOS transistors in a parallel manner, the potential of a node is provided to the P type MOS transistor and the N type MOS transistors, while the potential of a node is provided to the P type MOS transistor and the N type MOS transistors, so that a one shot pulse having a substantially identical waveform can be generated either when an input clock .phi..sub.IN changes its level from an 'H' level to an 'L' level or from the 'L' level to the 'H' level.

Pulse generating circuit for semiconductor device

In a DRAM having two I/O lines commonly provided for reading and writing data and an amplifying circuit for providing a read data signal by amplifying potential difference between the two I/O lines, a potential difference control circuit 8 is provided which includes detecting circuits each having a parallel connected circuit of two MOS transistors each being diode-connected, and a switch circuit which is rendered conductive only at data reading. Since the maximum value of the potential difference between the two I/O lines during data reading is controlled to several times that of the threshold voltage of a MOS transistor, the time necessary for equalizing the I/O lines at data reading can be reduced. Consequently, the speed of change of the output potential of the amplifying circuit changing to the potential corresponding to the data stored in the memory cell MC is increased, and therefore the access time is reduced.

Semiconductor memory device with restricted potential amplitude of data

Each driver circuit included in a word driver includes a transfer transistor and a driver transistor. A voltage of a predetermined voltage lower than a threshold voltage of the transfer transistor plus a power supply voltage is applied to the gate of the transfer transistor in an active period.

Semiconductor memory device having a word driver

A semiconductor memory device includes a memory cell array block (1; MB1 to MB16) having a first column group (area I) and a second column group (area II). The device also includes sense amplifiers (10-1, 10-2, 10-3 . . . ) provided for each column to detect and amplify a read-out voltage on associated columns. The device further includes a control circuit (20) for activating the sense amplifiers for the first column group and the sense amplifiers for the second column group at different timings to reduce peak current in sensing operation. The control circuit operates in response to a column designating signal to activate first the sense amplifiers for the column group including a column connecting thereto a selected memory cell. The column designating signal includes an externally applied column address bit. The column address bit is supplied to the device simultaneous with row address bits in an address multiplexing memory device. The first column group (BL0, BL0, BL2, BL2) includes a plurality of bit line pairs having at least one twisted portions. The second column group (BL1, BL1) includes a plurality of bit line pairs having no or one or more twisted portion. Bit line pairs of the first column group and bit line pairs of the second column group are arranged alternately.

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Hyogo, Japan

Kenji Tokami