National Institute of Advanced Industrial Science and Technology

Other

Agency of Industrial Science and Technology

Kddi Corporation

Agency of Industrial Science and Technology Ministry of International

Duaxes Corporation

Evolvable System Research Institute, Inc.

Bits Co., Ltd.

Kenji Toda

Tetsuya Higuchi

Masahiro Murakawa

Eiichi Takahashi

Toshihiro Katashita

Mitsugu Nagoya

Kazumi Sakamaki

Hiroyuki Yokoyama

Yoshinobu Uchibori

Yohei Hori

Yasunori Terashima

Yosuke Iijima

Toshio Shimada

Takeshi Inui

Masahiro Yasuda

Osamu Morikawa

Tadamasa Takayama

A network system by the present invention can quickly detect viruses and does not easily become a new cause of vulnerability. A packet data comparator branches inputted packet data into three branches, and includes an additional pattern matching unit which compares the branched data with the stored data and performs matching with collation patterns stored in a rewritable storage area, a fixed pattern matching unit which compares the branched data with the stored data and performs the matching with a logical operation configured with known collation patterns, a notification packet matching unit which compares the branched data with the stored data and finds a notification packet, and an identity detection aggregation unit which aggregates results from the respective matching units. Moreover, a virus filter, a virus checker, and a secure network system are realized by using the present invention.

Packet data comparator as well as virus filter, virus checker and network system using the same

Network device testing equipment capable of testing network devices using small size packets and for a transferring ability and a filtering ability at a media speed is described. A configuration is adopted in which a Field Programmable Gate Array (FPGA) included in a transmitter or receiver on one or both of transmitting and receiving sides is connected directly to a physical layer chip of a network and computers on both the transmitting and receiving sides are connected thereto. Each of the FPGAs of the transmitter and receiver has a circuit which has an integrated function of transmitting a packet pattern generation function and a packet-receiving function, thereby enabling a test and an inspection in real time. When inspecting the filtering function, a hash table storing therein a hash value and a list of occurrence frequencies for hash values is utilized. In order to avoid the hash values of different packets from having a same value, the hash function is configured so as to avoid that the same hash value is given to different packets or, when packet values have a common hash value, the packet is re-shaped into a packet having a different hash value.

FPGA-based network device testing equipment for high load testing

An image display apparatus for displaying image signals of a form of packets incorporating display position information includes a combination of unit display devices so as to acquire translational objectivity. Each of the unit display devices including a receiving part for receiving image signals, a processing part for dividing input image signals into those falling inside and those falling outside a range for display or those subject to or those not subject to display based on the display position information and serving to process display positions of the image signals falling outside the range for display or not subject to display, an output part for outputting the processed image signals along an axis of translational objectivity to a subsequent unit display device, and a display part for displaying the images falling in the range for display, the image display apparatus displaying the image signals as a whole, with the image signals processed sequentially with the unit display devices.

Image display apparatus

An electronic media communication apparatus is provided in which encryption keys and decryption algorithms are provided as circuits concealed in logic programmable devices. When the client requests delivery of electronic media, the server individually encrypts the electronic media and delivers the encrypted electronic media to the client. In the client, an electronic media specific circuit section uses logic circuit data received via a client data communication section to generate an electronic media specific logic circuit. Then, a logic circuit configuration section combines the logic circuit with a terminal specific circuit section uniquely implemented for the client to form an electronic media security circuit section. The original digital content can then be generated by inputting the encrypted electronic media stored in a storage unit to the electronic media security circuit section. Correct decryption is only possible when the electronic media specific circuit section and the terminal specific circuit section are used together in combination.

Electronic media communication apparatus

A CRC value calculator enables throughput to be improved while keeping down the increase in the size of the circuitry. This is achieved by using (n+1) basic CRC circuits to configure a CRC value calculator in which the width of the data processed during one clock cycle is m2bits. For example, when m2bits is the data width processed per calculator cycle, the CRC value calculator of this invention is configured by using selectors to serially connect a CRC circuit that processes every m2bits, a CRC circuit that processes every m2bits, . . . , and a CRC circuit that processes every m2bits. This configuration makes it possible to calculate a correct CRC value even when the remainder of an input network frame is not a multiple of m2bits. Selectors are used to select CRC circuit output according to process data width. Reduction of the operating frequency is avoided by using registers to form a pipeline between CRC circuits.

Cyclic redundancy checking value calculator

A digital system that performs a specified function by performing digital processing according to one or more clock signals is provided with a plurality of delay elements which are respectively inserted in a plurality of clock circuits that supply the clock signals in the digital system and each of which is composed of a circuit element that changes a delay time according to a value indicated by a control signal, and a plurality of holding circuits that hold a plurality of control signals to be given to the plurality of delay elements. In the plurality of holding circuits, a value of the control signals held by these holding circuits is changed by external devices according to a probabilistic search technique so that the digital system operates correctly in relation to operation timing.

Timing adjustment of clock signals in a digital circuit

In a computer system, when data for a register assigned to a current process arrives at a processing element, an instruction for loading this data is automatically inserted into an instruction sequence to be fetched by an instruction fetch unit provided in the processing element, thus synchronizing of data on registers is enabled. In addition, when data for a register assigned to a process which had previously been suspended and is not the current process arrives at the processing element, the data is written to a corresponding save area allotted in local memory for that register. Suspension of a process occurs at a point in time at which a register assigned to that process is accessed by an instruction but no data is yet present in the register and when this process suspension occurs, the process to be executed is switched to another process. When a register to which data arrives was the cause of a process suspension, that process which had been suspended is re-registered as an executable process and furthermore the data which arrived in the save area will be unsaved to the corresponding register.

Method by which packet handler inserts data load instructions in

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Tsukuba, Japan

Kenji Toda