Matsushita Electric Industrial Co., Ltd.

Tower Partners Semiconductor Co., Ltd.

Kenji Tateiwa

Tokuhiko Tamaki

Hiroshige Hirano

Takayuki Yamada

Ichiro Nakao

Genshu Fuse

Mitsuhiro Ohkuni

Tomoyuki Sasaki

Yasuo Sakurai

Hideo Nikoh

Hiroaki Kuriyama

Shunsuke Kugo

Koichi Kawashima

Hideaki Shimoda

An active region includes a body region in which first and second transistors are formed, a connection portion to which a potential of the body region is connected, and a lead portion that connects the body region and the connection portion. Source regions or drain regions of the first and second transistors formed in the body region are provided in a common region. Each of the lead portions extends from a corresponding channel region such that the lead portions are isolated from each other, and a gate electrode extends thereon. A width of the lead portion is narrower than a distance between corresponding ones of contact portions of the source regions and the drain regions of the first and second transistors. A width of the connection portion is equal to or narrower than a gate width of the gate electrode extending on the lead portion.

Semiconductor device

Variations in the size of a linear pattern resulting from difference in mask pattern layout are prevented by setting the perimeter of the linear pattern per unit area in a specified range irrespective of the type of a semiconductor integrated circuit device or by adjusting a process condition in accordance with type-to-type difference in the perimeter of the linear pattern per unit area.

Semiconductor integrated circuit device and method for fabricating the same

After an organic bottom anti-reflective coating (,) is deposited on an underlying film (,), a resist pattern (,) is formed on the organic bottom anti-reflective coating (,). Dry etching is performed with respect to the organic bottom anti-reflective coating (,) masked with the resist pattern (,) to form an anti-reflective coating pattern. The dry-etching of the organic bottom anti-reflective coating (,) is performed by using etching gas containing gas having the S component such as SO,/O,-based etching gas or COS/O,-based etching gas.

Pattern formation method

Liquid water drops are formed around particles situated on a substrate and diffuse laser light patterns are intensified by the liquid water drops to make it possible to detect minute particles of 0.1 .mu.m and less in dimension.

Method of inspecting particles on semiconductor devices

A method for fabricating a semiconductive device is described, wherein a semiconductive substrate having a thermally shrinkable, refractory metal silicide thin film is provided, on which an insulating film on the metal silicide thin film is formed. The metal silicide thin film is thermally treated in an atmosphere containing hydrogen. By this, no morphological degradation is observed in the silicide thin film without an increase of the resistance.

Method for fabricating a semiconductive device comprising a refractory

Disclosed is a method for burying a step in a semiconductor substrate in which (1) SiO.sub.2 layer is formed on a lower part of the step, (2) photoresist layer with equal thickness to the height of the step on the SiO.sub.2 layer at a portion corresponding to the lower part of the step, (3) sputter-SiO.sub.2 layer is formed by sputtering on the photoresist layer and SiO.sub.2 layer, (4) another photoresist layer is formed on the sputter-SiO.sub.2 layer, (5) the another photoresist layer and sputter-SiO.sub.2 layer are removed, and (6) the SiO.sub.2 layer and photoresist layer are removed. By this method, semiconductor substrate with flatness of within 50 nm in a 6-inch wafer can be obtained.

Growing community of inventors

Osaka, Japan

Kenji Tateiwa