Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kenji Shimazaki

Hiroyuki Tsujikawa

Shouzou Hirano

Takahiro Ichinomiya

Kazuhiro Sato

Hiroshi Benno

Masatoshi Sawada

Takashi Mizokawa

Mitsumi Itoh

Shozo Hirano

Junko Honma

Seijirou Kojima

Tatsuo Ohhashi

Keiichi Kusumoto

Kazuyuki Nakanishi

Masao Takahashi

Takashi Ando

Nobufusa Iwanishi

Tetsurou Toubou

Masanori Tsutsumi

Hisato Yoshida

Kazuhiro Satoh

Naoki Amekawa

Masaaki Hirata

Seijiro Kojima

Kasumi Hamaguchi

Hidetoshi Narahara

Kaori Matsui

Ritsuko Kurazono

Shingo Miyahara

A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width Wlarger than a cell width of cell A-1, but gate length Lof a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width Wequal to a cell width of cell B-1, but has a MOS transistor having large gate length L. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.

Semiconductor integrated circuit device having a plurality of standard cells for leakage current suppression

It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.

Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device

Operation analysis is performed for a semiconductor integrated circuit designed by using substrate bias control technology. Power supply potential and substrate potential are analyzed by using circuit information of the semiconductor integrated circuit, and from obtained power supply potential waveform information and substrate potential waveform information, potential difference information indicating a difference value between the power supply potential and the substrate potential is obtained. On the basis of this potential difference information, effects on circuit delay due to substrate noise are analyzed using a delay library showing a relationship between the difference value and the effects on circuit delay. Further, a determination is performed as to whether the difference value exceeds a predetermined difference restriction value.

Operation analysis method of semiconductor integrated circuit

In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.

Method of designing a semiconductor integrated circuit

Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device

An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

Design method for semiconductor integrated circuit suppressing power supply noise

There are contained the step of forming voltage waveform information by calculating a voltage waveform of each instance of a semiconductor integrated circuit at a power-supply terminal based on circuit information and analyzing the voltage waveform of each instance, the step of forming voltage abstraction information by abstracting the voltage waveform information, and the step of calculating a delay value of the instance based on the voltage abstraction information.

Operation analyzing method for semiconductor integrated circuit device, analyzing system used in the same, and optimization design method using the same

The resistance value of a supply line (Rline), the resistance value of a decoupling capacitor (Rcap), and the resistance value of a transistor (Rmos) are separately calculated from mask layout information of a semiconductor integrated circuit. The resistance value between external terminals (Ri) is calculated from the resistance value Rline, the resistance value Rcap, and the resistance value Rmos.

Method for estimating EMI in a semiconductor device

In a gate-level logic simulation, a change in electric current is calculated from event informationoutput from a logic simulatorthrough use of a current waveform calculation section. The thus-calculated change in current is subjected to FFT processing through use of an FFT processing section, thereby determining a frequency characteristic of EMI and enabling EMI analysis.

Method of analyzing electromagnetic interference

In contrast with a known dynamic gate-level simulation method, a method of analyzing electromagnetic interference (an EMI analysis method) according to the present invention enables estimation of EMI noise, by means of calculating signal propagation of each node through use of the signal propagation probability technique, and calculating variation time of each node through use of 'the Static timing analysis technique'. In short, the present invention is characterized in calculating a frequency characteristic from the relationship between toggle probability of each node and delay in each node.

A method of analyzing electromagnetic interference in which an amount of electromagnetic interference from an LSI is analyzed, wherein the method includes: an equivalent power source current information calculating step of calculating information of an equivalent power source current flowing in a power source current, from circuit information of the LSI chip; an estimating step of considering at least one of power source information of a power source for supplying a current to the LSI chip, package information of a package for the semiconductor chip, and measurement system information of a measurement system for measuring characteristics of the semiconductor chip, as analysis control information, and of estimating total information in which the analysis control information is reflected in the circuit information, as an equivalent circuit; and a total information analyzing step of performing analysis in accordance with the total information which is estimated in the estimating step.

Method and apparatus for analyzing electromagnetic interference

An electromagnetic disturbance analysis method for analyzing an external noise to a semiconductor integrated circuit includes an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.

Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the method

A method for optimizing electromagnetic interference (EMI) comprising: an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation; a step of selecting an instance with a large quantity of noise in said EMI analyzing step; and a step of adjusting a driving capability of said instance so that it is lowered to an extent that a delay does not occur in a signal timing of said instance selected. In order to optimize the analyzed EMI, the portion for which optimizing is required is extracted, and such a measure as increasing the area where the decoupling capacitance is created is implemented for this portion in a necessary degree. Further, by changing the aspect ratio of the block, changing the block position or changing the cell line, the decoupling capacitance can be easily created at the most efficient inserting position.

Method for optimizing electromagnetic interference and method for analyzing the electromagnetic interference

A method of analyzing an electromagnetic interference amount of an LSI includes an equivalent impedance information calculating step of calculating and estimating equivalent impedance information based on circuit information of an LSI chip and package information of the LSI chip, and an electromagnetic interference noise calculating step of calculating an electromagnetic interference noise based on the equivalent impedance information.

Electromagnetic interference analysis method and apparatus

A method for calculating a power consumption library on a gate level in a large-scale transistor circuit. The method includes: dividing a circuit network into a partial circuit network by a gate terminal of a transistor, calculating a relation of an input logical value to an output logical value in a partial circuit; calculating a relation of an output logical value to an input logical change in an output wiring between partial circuits, based on a partial circuit connection and a relation of an input logical value to an output logical value in a partial circuit; measuring a partial circuit power consumption by using an input logical change in each partial circuit; and regarding the sum of a power consumption at each partial circuit corresponding to an input logical change as a power consumption in a circuit network. The method also provides for reuse when a current path is the same in a circuit input logical change. The calculation also involves regarding the transistor as the same when a transistor with the same current characteristic is arrayed in the same order on the path even if a current path is different.

Growing community of inventors

Hyogo, Japan

Kenji Shimazaki