Mitsubishi Denki Kabushiki Kaisha

Matsushita Electric Industrial Co., Ltd.

Sanyo Electric Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Sharp Corporation

Other

Mitsubishi Electric Corporation

Kenji Shima

Shinji Komori

Hiroaki Terada

Hiroaki Nishikawa

Hajime Asano

Masahisa Shimizu

Souichi Miyata

Katsuhiko Asada

Satoshi Matsumoto

Hiroki Miura

Tetsuo Yamasaki

Yoshie Inaoka

Masahiro Hibino

Hidehiro Takata

Youichiro Nishikawa

Shuji Hara

Mitsuo Meichi

Toshiyuki Tamura

Mitsuo Shimotani

Shoichi Washino

Hirono Tsubota

Akihiro Tsumori

Shin-ichi Yoshida

Shunji Hine

Soichi Miyata

Niroaki Nishikawa

Setsuhiro Shimomura

Toshiya Okamoto

Yukinobu Nishimura

Minoru Ozaki

Yoshiaki Kanno

Takeshi Mitsui

Fumiyasu Asai

Koichi Munakata

Shin'ichi Yoshida

Takeshi Fukuhara

Yoshio Sakuta

Syoichi Washino

Katushiko Asada

A power line communication apparatus includes power lines disposed independently and individually, for connecting various loads to a battery by way of fuses, respectively, an inductor disposed at an end portion of each of the above-mentioned power lines on a side connected to the above-mentioned battery, and an information unit for transmitting information by way of each of the above-mentioned power lines.

Power line communication apparatus

A file management apparatus includes a file storage portion and a manipulation portion. The file storage portion stores a plurality of files therein. Each file includes one or more data structures. Each data structure includes one or more elements. The file storage portion further identifies each file with a file identifier and identifies each data structure within the file with an internal identifier and with the number of data structures contained in the file. The position of each data element and the number of data elements within a data structure are also identified. The manipulation portion manipulates the structure of the data stored in the file storage portion by employing the file identifier, the data structure identifier, and element position.

File management apparatus permitting access to portions of a file by

A program developing system includes a plurality of graphic editors representing specification definition information a user inputs in representation formats different from each other and a mutual conversion unit for converting specification definition which the user described with a graphic editor into a representation format of another graphic editor. The mutual conversion unit activates another graphic editor to allow input of specification definition by the converted representation format. The graphic editors can hierarchically represent specifications and allows specification description at an arbitrary level. The program developing system includes a parts management unit for registering description of semantically completed specification definition as parts and an execution unit for extracting executable program structure from the specification definition information represented by graphic editors and producing an executable program The executable program reserves the hierarchical structure in the specification description by the user. The execution unit executes a program at an arbitrary level and shows the execution results to the user. By execution and verification of the program at an arbitrary level, the user can know whether a program satisfying the specification is produced or not at a sub program level, which improves the program developing efficiency.

Program developing system allowing a specification definition to be

A signal processing apparatus enjoying a remarkably enhanced operation speed while ensuring accurate control capability due to data holding and learning control includes an A/D converter for converting an analog signal into a digital signal, a packet interface for generating a packet on the basis of the digital signal, a timing port controller for controlling the timing of operation of the A/D converter and generating output data on the basis of the packet, a power supply interruption detecting circuit for detecting a decrease in source voltage to thereby generate a power supply interruption detecting signal, and a data flow processor including a data store and a data flow loop for processing the packet in accordance with tag information contained in the packet. The data flow processor responds to the power supply interruption detecting signal to save electric power from consumption and hold the content of the data store.

Signal processing apparatus for performing high speed arithmetic

A data-driven type computer system including an input limiting section for monitoring a current number of packets existing in the circular pipeline of the system while being processed. The input limiting section is adapted to control packets from being inputted from the external unit when the current number of packets exceeds a specified threshold value which is greater than a minimum packet number existing in the circular pipeline and which allows the attainment of the highest possible throughput of the system. The input limiting section further includes a predictive control unit to preliminarily analyze a current data flow graph to be processed in the system and also to take order in rank a possible rate of increase in the quantity of packets generated by a copying operation as well as a possible rate of reduction in the prior processing by the system. While being stored once for buffering by an input buffer, variation in the current quantity of deposited packets is predicted by the predictive control unit every time when packets are entered from an external source or from the output section, so that they are prevented from being entered by the input limiting section when the current quantity of deposited packets is in excess of the preset limit of the hardware.

Data-flow processing system having an input packet limiting section for

A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.

Data flow processor with data processing and next address determination

A system for actualizing a process of a multi-generation packet by managing the generations of the packet inputted in a firing process module of a data driven type processor. The firing process module includes a generation management unit for rearranging the disk order of a sequence relationship associated with a periodic circulation of the generation numbers of a packet inputted. Further included is a subsystem for separating an address space in hashing when obtaining an address of a queuing memory of the firing process module.

Data driven type processor including a generation management system

An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.

Associative storage for data packets including asynchronous,

Processor for control including a data-flow processor

An apparatus for manipulating a relational data base includes a unit for describing input data in a table format, a unit for describing all the operational manipulation with respect to the input data in a non-text format, and a unit for outputting data by referring to the relational data base based on the described input data and operational manipulation. The input data of a table format includes an input table and an output table. The input table includes an operational description region and the output table includes a region wherein a map relation between the respective items of the input and output table is described. The manipulation contents are described in the operation manipulation description region and the map relation description region. The operation flow is described and defined by a connection line with directiveness. The apparatus enables description of all the operational manipulation in a graphical manner in a non-text format, providing a user with data base manipulation environment with excellent understandability and operability.

Manipulating data in a relational data base having operational

Disclosed is a data processor incorporating a timer function for measuring the time on the basis of a circulation time of a timer packet circulated through a circular pipe line for circulating said packet, a timer function for measuring the time by comparing the time information read from a time information reading means controlled by a process code having a packet with a preset time value and a timer function for measuring the time by comparing a timer packet given from outside at a predetermined timing with the preset time value.

Data-flow processor having timer control mechanism for effecting time

A data flow processor which is so constructed that the destination node number in a program memory is stored at a relative address from, for example, a stored address of the present instruction, and a storing address for the next instruction is obtained by adding the relative address of the next instruction to the address of the present instruction. Hence, an amount of data of storing address of instruction to be executed next executed and included in the respective instructions is reduced, whereby an amount of hardware at the program memory is reduced and the memory access time is contracted.

Data flow processor with next destination node determination

A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.

Parallel processing development system with debugging device includes

A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.

Reduced power pipelined static data transfer apparatus

In a data flow machine, a program stored in advance is read out based on a tag included in a packet when the packet including first data is inputted from an external portion. Then, an instruction packet is formed by the content read out as a new tag and the first data, so that the instruction packet is outputted. Second data including the same tag as that included in the first data of the instruction packet read out from the program memory is detected. Firing processing is performed with respect to the first data and the second data as a pair and arithmetic processing is performed according to the instruction as a part of the tag included in an arithmetic packet, so that the arithmetic packet is outputted as a packet. The tag included in the packet is determined and the packet is outputted to an external portion or is inputted again to the internal portion.

Data flow machine

Growing community of inventors

Hyogo, Japan

Kenji Shima