Hitachi, Ltd.

Hitachi Information Technology Co., Ltd.

Kenji Shigeoka

Tatsuki Ishii

Yoshihiro Iwai

Hirotake Tokuyama

A delay diagnosis method is proposed that can avoid design steps from being retraced or repeated uselessly due to defective delay when we design a semiconductor integrated circuit including a plurality of blocks. This delay diagnosis method has the steps of inputting logic information and floor plan information, finding the number of start points connected to the end point of a path from the logic information, computing the logic stage number of the path from the number of start points, finding block-to-block distances from the floor plan information, computing intra-block delays from the logic stage number and gate unit-value delays, computing inter-block delays from the block-to-block distances and routing unit-value delays, and diagnosing if the delay of the path after logic synthesis can be converged within a target path delay from the relation among the computed intra-block delays and inter-block delays and the target path delay.

Delay diagnosis method for semiconductor integrated circuit, computer program product for diagnosing delay of semiconductor integrated circuit and computer readable recording medium recording program thereon

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Nakai, Japan

Kenji Shigeoka