Nec Corporation

Gold Charm Limited

Kenji Sera

Naoki Matsunaga

Hiroshi Tsuchi

Fujio Okumura

Hiroshi Okumura

Takahiro Korenari

Mitsuasa Takahashi

Isao Sasaki

Hiroshi Kanou

Tadahiro Matsuzaki

Tamaki Fukata

When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region of a part of the n-channel TFTs and a part of the p-channel TFTs. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs, which can reduce the off-current, in logics and switch circuits and for forming low-VT TFTs, which can enlarge the dynamic range, in analog circuits to improve the performance of a thin film semiconductor.

Thin film semiconductor device and manufacturing method

A TFT array substrate is provided with an auxiliary capacitance that has a plurality of lower electrodes disposed for each pixel in the row and column directions below a pixel TFT and connected to the drain area of the corresponding pixel TFT. The distances Land Lbetween separation areas formed between the lower electrodes adjacent in the row direction and the channel areas of the two pixel TFTs that correspond to the lower electrodes are substantially equal to each other. The distances Land Lbetween separation areas formed between the lower electrodes adjacent in the column direction and the channel areas of the two pixel TFTs that correspond to the lower electrodes are substantially equal to each other. Furthermore, an upper electrode is disposed above the separation areas.

Thin-film transistor array substrate and liquid crystal display device

At least either above or below a memory transistor formed on an insulating substrate, a shielding layer which has an area larger than that of the semiconductor layer of the memory transistor and has either an electromagnetic wave shielding effect or a light shielding effect or both of these is provided, and by this shielding layer, electromagnetic waves or light is prevented from entering the semiconductor layer. Or, the regional area of at least one of the gate and the charge accumulation layer of the memory transistor is made larger than the semiconductor layer to prevent electromagnetic waves or light from entering the semiconductor layer by the gate or the charge accumulation layer.

Nonvolatile semiconductor memory having a charge accumulation layer connected to a gate

A light shielding film capable of shielding against light entering an active layer of a TFT and electroconductive is formed on the lower layer side of the active layer. Electrical stress is applied by causing a current in an insulating film between source and drain electrodes and the light shielding film to introduce a trap level at a density at least about 5&#xd7;10/cminto a source region and a drain region in a surface portion of the active layer on the light shielding film side.

Thin-film transistor with set trap level densities, and method of manufactures

A thin film transistor is provided including an active layer, in which a source region and drain region are formed, a first light-shielding film shielding a light incident on the active layer, and a second light-shielding film between the active layer and the first shielding film. A carrier concentration of at least surface portion of the second light-shielding film which opposes the active layer is about 10/cmor less.

Thin film transistor, TFT substrate and liquid crystal display unit

A method of fabricating a thin film transistor including an electrically insulating substrate, a semiconductor layer formed on the substrate, and source and drain electrodes formed above source and drain regions formed in the semiconductor layer, the source and drain electrodes being composed of aluminum or aluminum alloy, the method including the steps of forming a gate electrode, implanting impurity ions into the semiconductor layer for forming the source and drain regions, forming an interlayer insulating film entirely over the substrate, forming contact holes throughout the interlayer insulating film such that the source and drain regions are exposed through the contact holes, forming an electrically conductive film composed of aluminum or aluminum alloy, in the contact holes for forming the source and drain electrodes, and thermally annealing the substrate at 275 to 350 degrees centigrade for 1.5 to 3 hours in inert atmosphere.

Method of fabricating thin film transistor

A TFT array substrate blocks light traveling toward active layers of the TFTs. A patterned first light-shielding layer is formed between a transparent plate and TFTs to overlap with the active layers of the TFTs. A patterned third light-shielding layer is formed to cover the TFTs on the opposite side to the plate with respect to the TFTs. The third light-shielding layer has the first parts extending along rows of the matrix and the second parts extending along the columns thereof. A patterned second light-shielding layer is formed between the first light-shielding layer and the TFTs. The second light-shielding layer has a light-absorbing property, which absorbs the light entering the inside of the substrate. A patterned fourth light-shielding layer may be additionally provided between the TFTs and the third light-shielding layer.

TFT array substrate and active-matrix addressing liquid-crystal display device

A thin-film semiconductor device is provided including a plurality of thin-film transistors (TFT) having different driving voltages formed on an glass substrate, wherein a gate insulator electric field at each of the driving voltages of the plurality of thin-film transistors is in a range of about 1 MV/cm to 2 MV/cm, and a drain concentration of p-type thin-film transistors (TFT) is in a range of about 3E+19/cmto 1E+20/cm.

Thin-film semiconductor device and liquid crystal display

A gate-overlap-drain structure is obtained by a single pair of a single impurity implantation process and a single laser anneal process, wherein the improved gate-overlap-drain structure includes lightly activated high impurity concentration regions exhibiting substantially the same function as the lightly doped drain regions, wherein the lightly activated high impurity concentration regions are bounded with high impurity concentration regions serving as source and drain regions. The boundaries are self-aligned to edges of a gate electrode. Side regions of the gate electrode overlap the lightly activated high impurity concentration regions.

Method of manufacturing a field effect transistor and a liquid crystal display using the same

Field effect transistor as well as liquid crystal display using the same

There is presented a liquid crystal display device having, on a transparent insulating substrate, an underneath light-shielding film, a thin film transistor (TFT) in which, over an interlayer film on said underneath light-shielding film, an active layer made of polysilicon, a gate insulating film and a gate electrode connected with the gate line are successively formed, a data line that feeds the data signals into said TFT, and a black matrix formed over said data line to cut off the incident light, with said active layer of the TFT being formed in the region where said gate line and data line intersect each other, wherein the underneath light-shielding film and the data line are formed to have substantially equal widths, at least, in said active-layer formation area.

Liquid crystal display device having light-shielding film and data line of equal width and manufacturing method thereof

A pair of lightly doped drain (LDD) regions are provided in a thin film transistor of each pixel of a thin film transistor substrate for a liquid crystal display device and a light shielding portion of a material having reflectivity lower than that of a metal and covering a portion or a whole portion of the LDD regions is provided so as to restrict an internal random reflection of light.

Thin film transistor for use in liquid crystal display device and method for manufacturing the same

In a method for forming a polycrystalline silicon (poly-Si) thin film on an inexpensive glass substrate, a cap film doped with a catalyst element is provided on an amorphous silicon (a-Si) film formed on the substrate. The a-Si film is transformed into the poly-Si film by irradiating an excimer laser beam on the a-Si film through the cap film. Thereafter, the cap film is removed from the poly-Si film together with the catalyst element precipitated therein.

Method for forming polycrystalline silicon film

After a polycrystalline silicon film is formed on a glass substrate, the first gate insulating film is formed on the polycrystalline silicon film and the polycrystalline silicon film and the first gate insulating film are patterned into a island shape. Next, impurities are doped into the polycrystalline silicon film through the first gate insulating film using a resist mask, thereby forming the first source-drain region in part of the polycrystalline silicon film. Further, the second gate insulating film is formed on the first gate insulating film and a gate electrode is formed on the second gate insulating film. Thereafter, impurities are lightly doped through the first and second gate insulating films to thereby form the second source-drain region. Thus, no high etching technique is required for the manufacture of a thin film transistor and occurrence of electrostatic damage to the gate insulating films is prevented, to thereby make it possible to improve production yield.

Growing community of inventors

Tokyo, Japan

Kenji Sera