Kabushiki Kaisha Toshiba

Kioxia Corporation

Research Center for the Prevention of Diabetes

Research Center for Prevention of Diabetes

Kenji Sakaue

Hiroshi Sukegawa

Shinya Takeda

Hitoshi Tsunoda

Toshiyuki Furusawa

Tatsuyuki Ishikawa

Masaru Ogawa

Takeshi Nakano

Masahiko Motoyama

Yoshihisa Kondo

Shinji Maeda

Yuichi Miyazawa

Yukio Ishikawa

Ryouichi Bandai

Atsushi Takayama

Hironori Nagai

Yasuaki Nakazato

Kazuhiro Ichikawa

Mikio Takasugi

Akihiko Ishihara

Minoru Uchida

Yosuke Kino

Akihito Touhata

Koichi Inoue

Takumi Sasaki

Kouji Saitou

Akira Aoki

Shingo Tanimoto

Reiko Sakaue

Hironori Uchikawa

Koji Ogura

Yasuro Shobatake

Yoshinari Kumaki

Yoshio Mochizuki

Yasuo Unekawa

Keiko Fukuda

Tarou Iwashiro

Noriyuki Moriyasu

Terufumi Takasaki

Edward Bandy Samigat

Tamio Saimen

Yutaka Tango

Taro Iwashiro

Sachiyo Miyamoto

A memory system including a plurality of nonvolatile memories and a controller. The controller is connected to the plurality of nonvolatile memories via a plurality of channels. The nonvolatile memory stores a first parameter indicating a delay value. The controller acquires the first parameter from the nonvolatile memory. The controller delays start timing of data transfer to the nonvolatile memory via a channel among the plurality of channels by a delay value according to the first parameter.

Memory system

A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.

Memory system and information processing system

According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

A memory system includes a nonvolatile memory, and a memory controller configured to control the nonvolatile memory. The nonvolatile memory stores a busy table. The memory controller loads the busy table and controls a chip enable signal for the nonvolatile memory based on the busy table.

According to one embodiment, there is provided a memory system including a controller, a plurality of memory chips, and a channel. The controller outputs a clock signal, a timing control signal and a data signal. Each of the plurality of memory chips includes at least a clock input terminal, a timing control input terminal, a timing control output terminal, a data input terminal and a data output terminal. The channel includes a loop bus which connects the controller and the plurality of memory chips in a ring shape. The controller is able to control operation timings of the memory chips by transmitting the clock signal and the timing control signal to the plurality of memory chips via the channel.

A memory controller includes a host interface circuit connectable to a host device by a bus conforming to a memory card system specification, a data buffer circuit including a buffer memory, a tag information generation circuit configured to generate tag information associated with a command received by the host interface circuit, and a first register in which the tag information generated by the tag information generation circuit is stored, and a second register into which the tag information stored in the first register is copied after the command is fetched from the host interface circuit for processing. When a read request is made from the host interface circuit to the data buffer circuit, the data buffer circuit returns read data stored in the buffer memory upon confirming that the tag information stored in the first register and the tag information stored in the second register match each other.

Memory controller, memory system, and control method of memory system

According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.

Storage device and data latch timing adjustment method

According to one embodiment, a memory system includes a memory cell array, first error correction part, second error correction part, and third error correction part. The memory cell array includes a first storage area in which 1-bit data is stored in one memory cell, and second storage area in which data of a plurality of bits is stored in one memory cell. When data is written to the first storage area, the first error correction part generates first parity data in the row direction on the basis of the data described above. The second error correction part corrects an error of the data described above on the basis of the first parity data read from the memory cell array. The third error correction part generates second parity data in the column direction on the basis of data of a plurality of pages.

Nonvolatile semiconductor memory system error correction capability of which is improved

According to one embodiment, an error correction decoder includes a storage unit and parity check circuit. The storage unit stores first reliability information corresponding to a hard decision result of each of a plurality of bits which form an ECC (Error Correction Code) frame defined by a parity check matrix, and second reliability information corresponding to a soft decision result of each of the plurality of bits. The storage unit includes a register configured to allow the parity check circuit to steadily read out at least the first reliability information. The parity check circuit executes parity checking of a temporary estimated word based on the first reliability information using the parity check matrix. The parity check circuit executes parity checking once or more before completion of row processing and column processing of the entire parity check matrix by a calculation circuit for each trial of iterative decoding.

Error correction decoder and error correction decoding method

According to one embodiment, a memory module which includes a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected, and a controller which receives write data from a host device.

In an error detection correction method of an embodiment, in decoding processing using a sum-product algorithm, which repeats processing of propagating reliability &#x3b1; from a check node set to correspond to a Tanner graph of a check matrix of a low density parity check code to a plurality of bit nodes connected to the check node, and processing of propagating reliability &#x3b2; from a bit node to a plurality of check nodes connected to the bit node, the check node includes a parity of two bits or more.

Error detection correction method and semiconductor memory apparatus

According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction.

Semiconductor storage device, memory control device, and control method of semiconductor memory

Growing community of inventors

Kanagawa, Japan

Kenji Sakaue