Rohm Co., Ltd.

Kenji Otani

Ko Takemura

Norio Fujii

Kiyotaka Umemoto

Koichi Inoue

Koichi Yamasaki

Satoshi Furuno

Fumihiko Ito

Yorinobu Murayama

The invention provides a differential current output unit that has a least number of capacitors and a minimized chip area on one hand, and on the other hand that is capable of providing a smoothly varying output current across a zero-crossing point in accord with an inputted difference input voltage. To do this, the differential current output unit is entirely formed of differential circuits and current mirror circuits having predetermined current mirror ratios. Thus, the unit has a stable output current characteristic. The unit has an inflow output transistor circuit and an outflow output transistor circuit that are operably separated by a delivery circuit. Thus, no penetration current will flow through the inflow- and outflow-output transistor circuits.

Differential current output unit

A method of fabricating a semiconductor integrated circuit device is provided. The device includes a protection circuit that connects to a terminal and has a protection diode and a current mirror circuit. The current mirror circuit includes first and second transistors having bases thereof connected together and emitters thereof connected together, so that emitters are connected to an anode of the protection diode. A method includes forming the anode of the protection diode; forming a cathode of the protection diode to surround the anode; forming a collector of the first transistor to surround about a half of the anode within a region surrounded by the cathode; forming a collector of the second transistor to surround about another half of the anode; and forming the bases of the first and second transistors as a common base substantially parallel to an edge of the collectors of the first and second transistors.

Method of fabricating semiconductor integrated circuit device having protection circuit

A power supply unit (system power supply IC) has a multiplicity of power supply circuits providing for different supply voltages. Should an abnormal condition take place in any of the multiple power supply circuits, the power supply circuit suffering the abnormality issues an abnormality detection signal that contains a power supply circuit number and an abnormality type, which signal is stored in a nonvolatile memory together with time data indicative of the time of reception of the abnormality detection signal before all the power supply circuits are disabled. Thus, this arrangement protects the system power supply IC and the loads connected thereto, and provides convenient means for analyzing the abnormality and replicating it if necessary, based on the abnormal power supply circuit number, abnormality type and time data stored in the nonvolatile memory.

Power supply unit having multiple power supply outputs

To a plurality of terminals are connected, one to one, a plurality of current mirror circuits each having a first load portion through which a first current flows when an overvoltage is applied and a second load portion through which a second current proportional to the first current flows. The first load portion of the current mirror circuit connected to one of the plurality of terminals is shared as the first load portions of the current mirror circuits connected to the others of the plurality of terminals. The shared first load portion includes an overvoltage protection circuit. The second load portions of the current mirror circuits connected to the plurality of terminals each include an overvoltage detection circuit for detecting the second current.

Semiconductor integrated circuit device incorporating overvoltage protection circuit

In a semiconductor integrated circuit device, a reference voltage is connected to one input terminal of an amplifier, and the voltage appearing on the output side is divided by a plurality of resistors and is negatively fed back to the other input terminal of the amplifier to control the output voltage. Here, according to an input code fed to the semiconductor integrated circuit device, switching devices are turned on or off correspondingly to vary how the resistors are connected and thereby control the voltage division factor. Thus, the output voltage is set according to the input code.

Variable-output-characteristic semiconductor integrated circuit device

A single semiconductor chip containing a control portion and a power portion including a power element associated with the control portion and a concave portion formed between the control portion and the power portion is mounted on a die pad so as to separate the control portion and the power portion. The die pad has a convex portion which is received in the concave portion and the semiconductor chip is divided to separate the control portion and the power portion by applying pressure to the chip or by applying laser beams, and the separated semiconductor chip portions are simultaneously bonded to the die pad.

Semiconductor integrated circuit device and lead frame therefor

A motor control apparatus for rotating a motor smoothly. A sine wave form which is an ideal wave form of a signal is stored, and the motor is driven by a signal having the ideal wave form obtained by correcting the period and the phase of the stored sine wave form. A comparator receives a detection signal which indicates the rotating state of the motor through an A/D converter, and obtains the correction values of the current period and phase. A wave form setting means corrects the set period and phase, generates a sine wave having the corrected period and phase on the basis of the sine wave data stored in a sine wave data region, and outputs a driving signal having the sine wave form through a D/A converter.

Motor control apparatus

A motor drive circuit, in which a first transistor at a drive stage, a second transistor at an output stage to be driven by the first transistor and a third transistor downstream the output stage for a short braking operation are formed in a common substrate or a common well of the substrate, a region of either a P type or an N type in either the substrate or the well is connected with the first transistor via a conductor so that a parasitic transistor is formed in which the substrate or the well serves as its base, whereby a current flowing from the first transistor to the second transistor during the short braking operation is sinked by turning on the parasitic transistor.

Growing community of inventors

Kyoto, Japan

Kenji Otani