Qualcomm Incorporated

Snaptrack Incorporated

Qualcomm Mems Technologies, Inc.

Obsidian Sensors, Inc.

Solsona Enterprise, LLC

Kenji Nomura

John Hyunchul Hong

Je-Hsiung Lan

Cheonhong Kim

Bing Wen

Tallis Young Chang

Yaoling Pan

Edward Chan

Chong Lee

Tze-Ching Fung

A method of manufacturing MEMS housings includes: providing glass spacers; providing a window plate; attaching the window plate to the glass spacers; aligning the glass spacers with a device glass plate having MEMS devices thereon; bonding the glass spacers to the device glass plate; and singulating the glass spacers, window plate, and device glass plate to produce the MEMS housings.

Capping plate for panel scale packaging of MEMS products

The present invention provides a vertical-type thin film transistor (TFT). The vertical TFT may comprise a source electrode and a drain electrode extending parallel to each other, with a semiconductor layer arranged in between the source electrode and the drain electrode. Two or more gate electrodes may be embedded in the semiconductor layer, the two or more gate electrodes being arranged parallel to one another. Each of the two or more gate electrodes may comprise a structure adapted to allow the flow of electrons therethrough. The structure of each of the gate electrodes may comprise one of a comb-like structure, a mesh structure, a perforated structure, a lattice structure, and the like. The structure may block a direct electric field between the source electrode and the drain electrode. The structure may allow the flow of electrons around and between elements of the structure.

Vertical thin film transistor with perforated or comb-gate electrode configuration

This disclosure provides p-type metal oxide semiconductor materials that display good thin film transistor (TFT) characteristics. Also provided are TFTs including channels that include p-type oxide semiconductors, and methods of fabrication. The p-type metal oxide films may be hydrogenated such that they have a hydrogen content of at least 10atoms/cm, and in some implementations, at least 10atoms/cm, or higher. Examples of hydrogenated p-type metal oxide films include hydrogenated tin (II)-based films and hydrogenated copper (I)-based films. The TFTs may be characterized by having one or more TFT characteristics such as high mobility, low subthreshold swing (s-value), and high on/off current ratio.

Hydrogenated p-channel metal oxide semiconductor thin film transistors

This disclosure provides thin film transistors (TFTs) including p-n hetero-junction structures. A p-n hetero-junction structure may include a junction between a narrow bandgap material and a wide bandgap material. The narrow bandgap material, which may be an oxide, nitride, selenide, or sulfide, is the active channel material of the TFT and may provide relatively high carrier mobility. The hetero-junction structures facilitate band-to-band tunneling and suppression of TFT off-currents. In various implementations, the TFTs may be formed on flexible substrates and have low temperature processing capabilities.

Tunnel thin film transistor with hetero-junction structure

Provided herein are methods of depositing p-type metal oxide thin films by atomic layer deposition (ALD). Also provided are p-type metal oxide thin films and TFTs including p-type metal oxide channels. In some implementations, the p-type metal oxide thin films have a metal and oxygen vacancy defect density of less than 10/cm. The p-type metal oxide thin films may be electrically active throughout the entire thicknesses of the thin films.

Atomic layer deposition of P-type oxide semiconductor thin films

This disclosure provides p-type metal oxide semiconductor thin films that display good thin film transistor (TFT) characteristics. The p-type metal oxide thin films include ternary or higher order tin-based (Sn-based) p-type oxides such as Sn (II)-M-O oxides where M is a metal. In some implementations, M is a metal selected from the d block or the p block of the periodic table. The oxides disclosed herein exhibit p-type conduction and wide bandgaps. Also provided are TFTs including channels that include p-type oxide semiconductors, and methods of fabrication. In some implementations, the p-channel TFTs have low off-currents.

Tin based p-type oxide semiconductor and thin film transistor applications

This disclosure provides methods and apparatuses for annealing an oxide semiconductor in a thin film transistor (TFT). In one aspect, the method includes providing a substrate with a partially fabricated TFT structure formed on the substrate. The partially fabricated TFT structure can include an oxide semiconductor layer and a dielectric oxide layer on the oxide semiconductor layer. The oxide semiconductor layer is annealed by heating the dielectric oxide layer with an infrared laser under ambient conditions to a temperature below the melting temperature of the oxide semiconductor layer. The infrared laser radiation can be substantially absorbed by the dielectric oxide layer and can remove unwanted defects from the oxide semiconductor layer at an interface in contact with the dielectric oxide layer.

Laser annealing technique for metal oxide TFT

A method of etching a glass substrate using an etchant that is reversibly activated to etch only in precise locations in which such etching is desired and is deactivated when outside of these locations. The method involves exposing a first side of the glass substrate to a mixture of chemical substances that includes a neutralized etchant that is photosensitive. The neutralized etchant is formed by reacting a neutralizer with an etchant. The method also includes transmitting light from a direction of a second side of the glass into the mixture of chemical substances. In response to exposure to this light, the etchant is reversibly released from a bond to the neutralizer to form the etchant on predetermined areas of the first side of the glass, wherein the predetermined areas are defined by the dimension of the light.

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San Jose, CA, United States of America

Kenji Nomura