Mitsubishi Denki Kabushiki Kaisha

Sony Semiconductor Solutions Corporation

Dai Nippon Printing Co., Ltd.

Kenji Noguchi

Shinichi Kobayashi

Tsuyoshi Toyama

Kenji Kohda

Nobuaki Andoh

Takeshi Nakayama

Kazuo Kobayashi

Yasushi Terada

Kazumasa Kohama

Makoto Yamamoto

Hiroaki Nagano

Yasuo Kanda

Takashi Tominaga

Yoichi Takahashi

Junji Fujikawa

Toshifumi Yokoyama

Yasutaka Morikawa

Mikio Oka

Yoshinori Kinase

Toshiaki Motonaga

Hiro-o Nakagawa

Masaya Uemura

Masahide Kaneko

Toshiyuki Koimori

Kei Maejima

Nobuaki Ando

Megumi Nakayama

A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.

Semiconductor device and electronic apparatus including the same

Provided is a semiconductor apparatus capable of enhancing the withstand voltage while suppressing the enlargement of the chip area. Provided is semiconductor apparatus including: a first terminal to which a high frequency signal is supplied; a second terminal from which the high frequency signal is output; first, second and third switch elements electrically connected in series between the first terminal and the second terminal; a first capacitor provided between the first terminal and a first node between the first switch element and the second switch element; and a second capacitor provided between the first terminal and a second node between the second switch element and the third switch element, in which the capacitance of the first capacitor is greater than the capacitance of the second capacitor.

Semiconductor apparatus and module

In one example, a signal processing circuit including a directional coupler and a termination part is disclosed. The directional coupler includes a main line as a transmission path of an RF signal and a sub-line constituting a coupled line together with the main line. The termination part includes devices connectable between ground and a first port at an end of the sub-line. The signal processing circuit switches, depending on a frequency of the RF signal, the devices of the termination part to be connected to the first port. The phase of a return signal of a signal input as a coupling signal to the termination part via the first port is opposite to the phase of an isolation signal supplied to a second port at the other end of the sub-line and connected to an output port of the coupling signal.

Signal processing circuit, signal processing module, and communication apparatus

A photomask is produced which enables the simplification of the steps of lithography. A photomask is provided with shielding patterns made of shielding metallic thin film on a transparent substrate, wherein the photomask further comprises translucent patterns mainly including tantalum of materials selected from tantalum silicide, tantalum oxide, tantalum nitride or mixture thereof.

Photomask

A circuit for detecting contact of a magneto-resistive (MR) head with a disk surface by properly sensing disturbance signals without being effected by noises using a simple configuration. The circuit for detecting contact of the MR head with the disk surface by sensing a disturbance waveform generated by MR head contact with the disk surface comprises a comparator for comparing a signal read out by MR head with a threshold level V.sub.th ; a pulse width limiting circuit for restricting a pulse width x, which is wider than the predetermined pulse width x.sub.1, to a pulse width x.sub.1 ; and a D flip-flop circuit in which an output signal of the comparator being applied to both D terminal and R terminal, and an output signal from the pulse width limiting circuit being applied to T terminal, and an output signal being obtained from an inverted output terminal QC.

Circuit for detecting contact of MR head with disk surface

A phase comparison circuit used in a phase locked loop circuit which realizes a stable phase locked loop circuit without changing the output frequency of a voltage-controlled oscillator, even if an input pulse is missing. The phase comparison circuit includes a circuit for generating a first pulse at each rising edge of an input signal, a circuit for generating a second pulse at each falling edge of the input signal, a circuit for generating a third pulse at each falling edge of a reference signal, a circuit for generating a first output signal from the first pulse and the second pulse, and a circuit for generating a second output signal from the first pulse and the third pulse. The output signals are not increased even if an input pulse is missing so that the operation of the phase locked loop circuit remains stable.

Phase comparison circuit for maintaining a stable phase locked loop

A nonvolatile semiconductor memory comprising an erase pulse generator, an erase pulse counter and an erase verify signal generator. The erase pulse counter counts erase pulses output by the erase pulse generator, and the erase verify signal generator generates an erase verify signal. The erase pulse counter keeps the erase verify signal generator inactive until the number of the counted erase pulses exceeds a predetermined count. Only erase operations are allowed to continue while erase verify operations are being suppressed, until the erase pulse count exceeds the predetermined count. The scheme shortens the erase time involved.

Semiconductor memory capable of reducing erase time

In a memory device in a bare chip state which is determined as fail by over erasing during a test at a wafer level, information indicating the presence of an over-erased memory cell is stored in a nonvolatile and readable manner into an identification memory circuit, and then memory cells in a memory cell array are restored to an erase state of an electrically neutral state by irradiation with an energy beam such as ultraviolet rays. A chip erased by the energy beam such as ultraviolet rays is assembled as an OTPROM (one-time programmable read only memory) and tested. At that time, a writing/erasing control circuit for controlling data writing into and data erasing in the memory cells is brought into an operation inhibited state in accordance with the information stored in the memory circuit. It is possible to reduce the rate at which fail products are produced by use of a flash memory which is determined as fail because of the presence of an over-erased memory cell as a one-time programmable memory device.

Nonvolatile semiconductor memory device and manufacturing method and

A semiconductor memory device having error checking/correcting functions includes a circuit (10) for generating a code for error checking/correcting based on information externally supplied and linking the information and the code to be transmitted to a memory cell array (1), and another circuit (11) for error checking and correcting read-out information from the information and the code which are read-out from the memory cell array so as to output correct read-out information. The code word generating circuit (10) and the error checking/correcting circuit (11) are formed of a masked ROM integrated on the same semiconductor chip (100) as that of the memory cell array (1) in the memory device.

Method of making a semiconductor memory device having error

The input data comprising binary data to be stored are converted into multi-state data. A voltage of a level based on the converted multi-state data is applied to a source region to perform write operation to a memory transistor. As a result, the threshold voltage of the transistor is set to a value corresponding to the potential of the source region. In read operation a drain current generated in the memory transistor is detected and the multi-state data corresponding to the current are obtained. These multi-state data are converted into binary data to be outputted as output data.

Non-volatile memory device capable of storing multi-state data

In a nonvolatile semiconductor device in which source metal interconnections for coupling to ground a source of a floating gate type memory transistor are commonly provided for each predetermined plurality of memory transistors, switching transistors are provided for each column for coupling to ground columns excluding the selected column when a single column is selected in response to an external column address. Each of the switching transistors operates in response to an inverted signal of an output of a column decoder. According to this structure, a variation in source potential of each memory transistor caused by the difference in source resistance associated with each of the memory transistors is reduced.

Nonvolatile semiconductor memory device with reduced variation in source

A semiconductor memory device having an error checking and correcting (ECC) circuit is disclosed. This memory device includes data lines (10-21) from an ECC data generation circuit and bit lines (30-41) connected to the adjacent memory cells in a memory array (1), which are selectively connected at specified connecting portions (51, 52). When predetermined test data is inputted in order to detect undesired contact or interference between the memory cells, checker pattern data can be written in all the memory cells. Thus, despite the fact that the memory device includes an ECC circuit, a complete and easy memory cell checking is carried out.

Semiconductor memory device having error checking and correcting circuit

A method for producing a mask ROM having an array of memory cells in which pn junctions obtained by introducing P-type impurities by ion implantation onto the surface of an N-type electrically conductive layers obtained in turn by introducing N-type impurities into the polysilicon layers are formed as memory cells in a matrix configuration. The polysilicon layers that are to be rendered into the N-type electrically conductive layers are previously monocrystallized by laser annealing. In this manner, the N-type electrically conductive layers into which P-type impurities are introduced by ion implantation at the time of formation of the pn junction are turned into a monocrystalline layer so that the surface of the N-type electrically conductive layers may be uniformly and easily converted into the P-type by this ion implantation. In short, the junction surface of the pn junction used as the memory cell becomes uniform. In this manner, the memory cell having desirable pn junction properties, that is, suited for practical application, may be produced easily.

Mask ROM having monocrystalline silicon conductors

An EPROM as a nonvolatile semiconductor memory device includes a semiconductor substrate 1, a gate oxide layer 3 formed on the surface of the semiconductor substrate 1, a plurality of floating gates 4a and 4b formed on the gate oxide layer 3 so as to overlap one another at the portions 4ab thereof with a gate oxide layer 14 sandwiched between the overlapping portions 4ab, and control gate strips 5 formed on a gate oxide layer 6 which overlies the floating gates 4a and 4b.

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Hyogo, Japan

Kenji Noguchi