Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Kenji Nishimoto

Yoshitaka Kinoshita

Masakazu Aoki

Kazumasa Yanagisawa

Hiromasa Noda

Hitoshi Tanaka

Takeshi Wada

Susumu Hatano

Yasushi Takahashi

Masayasu Kawamura

Shin'ichi Ikenaga

Fujio Yamamoto

Jun Kitano

Michihiro Mishima

A bootstrap circuit is provided for a word line selector for setting word lines connected with dynamic memory cells at a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage. The bootstrap circuit generates a bootstrap voltage which is given a difference substantially equal to the threshold voltage of address select MOSFETs with respect to the high level of bit lines connected with the memory cells, and feeds the bootstrap voltage to the selected word lines. The bootstrap circuit is activated in synchronism with a clock signal at a timing corresponding to an action mode designated by a command in an SDRAM before a precharge action, thereby changing the select level of the word lines from the first voltage to the bootstrap voltage.

Dynamic RAM having word line voltage intermittently boosted in

An X address buffer for generating an internal address signal by capturing an X address signal input from an address terminal is brought into an operating state before an external control clock is input. A redundancy address comparator for detecting a match/mismatch signal by comparing the generated internal address signal with a stored X-system defective address is used as a static circuit. Thereby, the redundancy address comparator starting operation is accelerated and as a result, acceleration of the reading operation is achieved.

Dynamic RAM provided with a defect relief circuit

Herein disclosed is a semiconductor integrated circuit for testing test data of two kinds of non-inverted and inverted statuses of all bits by itself with a prospective data of one kind to compress and output the test results. The semiconductor integrated circuit includes a decide circuit 25 for deciding a first status, in which the prospective data latched by a pattern register and the read data of a memory cell array are coincident, a second status, in which the read data is coincident with the logically inverted data of the prospective data, and a third statuses other than the first and second statuses through an exclusive OR gate to generate signals of 2 bits capable of discriminating the individual statuses. These statuses are informed to the outside of the semiconductor integrated circuit in accordance with high- and low-levels and a high-impedance.

Semiconductor memory device

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Urawa, Japan

Kenji Nishimoto