Ricoh Company, Ltd.

Kenji Nishihara

Tohru Haruki

Koichi Sogawa

Tadao Uehara

Shouji Tochishita

Tetsuya Okada

Akinori Suzuki

Masanori Miyata

Yuuichi Kohno

Hidetsugu Miyake

Taro Usami

Shisyo Chin

Hiroaki Teratani

Kiyotaka Ishibushi

Kiyoshi Yano

Minoru Ohtomo

A method of manufacturing a semiconductor device is disclosed that includes a semiconductor wafer having a main surface including a device chip area, a peripheral area encompassing the device chip area, and a blank area situated between the device chip area and the peripheral area. The method includes the steps of coating the entire main surface of the semiconductor wafer with a positive photosensitive resist, defining an additional exposure area in the blank area, conducting a first exposure process on the peripheral area and the additional exposure area, conducting a second exposure process on the device chip area, removing resist remaining on predetermined areas of the device chip area, the peripheral area and the blank area after conducting the first and second exposure processes for forming a resist pattern, and dry-etching the main surface of the semiconductor wafer by using the resist pattern as a mask.

Method of manufacturing semiconductor device

A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R, R, R, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T, T, T, . . . , Tx represent the polishing time T required for achieving a target film thickness when performing the flattening process by polishing each of the interlayer insulating films coating the projecting patterns; and a step of calculating, with the use of a formula T=(R&#x2212;b)/a, the polishing time T for the interlayer insulating films coating the projecting patterns having the area ratio R.

Chemical mechanical polishing method and chemical mechanical polishing device

A semiconductor wafer is disclosed that includes a substrate; a plurality of device chip areas formed on the substrate; a plurality of scribe lines formed in a lattice-like manner on the substrate, the scribe lines being provided so as to separate the device chip areas from each other; a blank area in which at least one alignment mark formed of a metal film for alignment of the semiconductor wafer is formed, the blank area being provided in an area different from the device chip areas; and a scribe area in which the alignment mark is prevented from existing, the scribe area being provided in each area where the blank area crosses the scribe lines.

Wafer, reticle, and exposure method using the wafer and reticle

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Hyogo, Japan

Kenji Nishihara