Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Electric Co., Ltd.

Kenji Natori

Fujio Masuoka

Mitsugi Ogura

Shinichi Takagi

Kazunori Ohuchi

Syuso Fujii

Shozo Saito

Junji Koga

Kaoru Nakagawa

Tohru Furuyama

A is a memory circuit including a plurality of ferroelectric capacitors arranged in a matrix, setting MOS field effect transistors for setting both electrodes of each of the ferroelectric capacitor at the same electric potential, and transmission MOS field effect transistors for transmitting information to the ferroelectric capacitors, and having a construction in which two word lines are provided corresponding to each line of the ferroelectric capacitors, one bit line is provided corresponding to each row of the ferroelectric capacitors, each of the transmission MOS field effect transistors is connected to one of the word lines and the bit line, and each of the setting MOS field effect transistors is connected to the other word line. Also disclosed is a memory circuit including memory cells each composed of each of ferroelectric capacitors arranged in a matrix and transmission MOS field effect transistors provided corresponding to the ferroelectric capacitors for transmitting information to the ferroelectric capacitors, line address decoders each provided corresponding to each group of the memory cells in each line for controlling the input and output of information to the ferroelectric capacitors, word lines provided corresponding to each group of memory cells in each line for selecting the line, and drive lines for commonly controlling the ferroelectric capacitors in the group of memory cells, and having a construction in which the word lines and the drive lines are connected to the line address decoders, and bit lines are provided corresponding to each row of the memory cells.

Ferroelectric capacitor memory circuit MOS setting and transmission

A nonvolatile semiconductor memory including multiple memory cells. Each memory cell comprises a FET TM having a ferroelectric insulation film and two MOS transistors T1 and T2 connected in series to the ends of the source-drain path of the FET, respectively. To write data into a memory cell, an electric field is applied in a predetermined direction between the gate and the substrate of the transistor TM. The electric field polarizes the gate insulation film of the transistor TM, which is made of ferroelectric material, in the direction, thereby writing data into the memory cell. In a data read mode, if the transistor TM is on, a current flows through the transistor TM, and the potential of a bit line to which the transistor TM is coupled decreases. In contrast, if the transistor TM is off, no currents flow through this transistor TM, and the potential of the bit line to which the transistor TM is coupled remains unchanged. Thus, the data stored n the memory cell can be discriminated by detecting whether the potential of the bit line corresponds to a '1' bit or a '0' bit.

Ferroelectric memory device

A memory circuit including a plurality of ferroelectric capacitors arranged in a matrix, setting MOS field effect transistors for setting both electrodes of each of the ferroelectric capacitor at the same electric potential, and transmission MOS field effect transistors for transmitting information to the ferroelectric capacitors, and having a construction in which two word lines are provided corresponding to each line of the ferroelectric capacitors, one bit line is provided corresponding to each row of the ferroelectric capacitors, each of the transmission MOS field effect transistors is connected to one of the word lines and the bit line, and each of the setting MOS field effect transistors is connected to the other word line. Also disclosed is a memory circuit including memory cells each composed of ferroelectric capacitors arranged in a matrix and transmission MOS field effect transistors provided corresponding to the ferroelectric capacitors for transmitting information to the ferroelectric capacitors, line address decoders each provided corresponding to each group of the memory cells in each line for controlling the input and output of information to the ferroelectric capacitors, word lines provided corresponding to each group of memory cells in each the line for selecting line, and drive lines for commonly controlling the ferroelectric capacitors in the group of memory cells, and having a construction in which the word lines and the drive lines are connected to the line address decoders, and bit lines are provided corresponding to each row of the memory cells.

Disclosed is a semiconductor memory device comprising an SOI substrate in which a semiconductor film is formed on a semiconductor substrate with an insulating film interposed therebetween. A memory cell structure is formed by a switching MOS transistor formed in the SOI substrate and an Esaki diode is positioned on the MOS transistor. The memory device also comprises a memory cell provided with a plurality of tunnel diodes connected to one of the impurity regions constituting the FET formed in the semiconductor substrate, and another memory cell provided with an Esaki diode formed in an self-alignment by a solid phase diffusion. In manufacturing the semiconductor memory device, the MOS transistor and the Esaki diode, which collectively form a memory cell, are integratedly formed one upon the other. The MOS transistor is formed in a semiconductor substrate using an SOI structure so as to prepare a memory cell which does not include a parasitic pn-junction.

Semiconductor memory device and manufacturing method thereof

In the semiconductor memory device of the invention, a normal voltage detecting circuit and a high voltage detecting circuit are connected to a terminal for the purpose of receiving a write enable signal. When a signal of normal level is supplied to the terminal, the circuit controls data read or write with respect to a memory cell array in accordance with the level of the write enable signal. An error correction code circuit is rendered operative, and a soft error generated in data read from the memory cell array is corrected. When a high voltage is applied to the terminal, the circuit sets the memory device in the read mode. The circuit detects application of the high voltage to the terminal and supplies a predetermined signal to an ECC control circuit. In response to the signal, the ECC control circuit stops the operation of the ECC circuit. Data without any correction of soft errors is output from the memory device, and testing of hard errors is simplified.

Semiconductor memory device having error detection/correction function

A MOS transistor integrated circuit device has at least one interconnection layer crossing the source and drain regions of a MOS transistor such that it overlies these source and drain regions. An electrical conductive layer is formed on the surface of at least one of the source and drain regions of the MOS transistor. The electrical conductive layer crosses the interconnection layer with an insulating layer therebetween such that it underlies the interconnection layer. The electrical conductive layer is separated from source and drain takeout electrodes and electrically insulated from the interconnection layer.

Semiconductor integrated circuit device

A dynamic type semiconductor memory device includes a memory cell having a capacitor for storing an amount of charge corresponding to data and, an n-channel MOS transistor to control charging and discharging to and from the capacitor, and a control unit to permit a read/write operation of the memory cell. The control unit of the memory device includes a drive circuit for generating turn on and turn off voltages, a charge pump circuit connected to the gate of the memory cell, and a switching element connected between the drive circuit and the gate of the MOS transistor.

Dynamic type semiconductor memory device

A semiconductor dynamic memory device includes a plurality of memories, row decoders for selecting the row of the memories, column decoders for selecting the column of memories, and sense amplifier circuits connected to the memories, respectively. The dynamic memory device further has a driving circuit for selectively activating some of the sense amplifier circuits in accordance with the content of a predetermined bit of row address data supplied to the row decoders.

Semiconductor dynamic memory device

The first and second intrinsic semiconductor layers of thickness d are formed on a P type semiconductor substrate, keeping a prescribed interval therebetween, whereby a groove of depth d may be made between these layers. A dielectric layer is formed in such a way that it may cover a base and sides of the groove and a surface of the intrinsic semiconductor layer. On this surface, a gate electrode formed of polysilicon exists. Diffusion regions of a source and a drain of depths X.sub.sj and X.sub.dj are formed, in the neighborhood of groove sides, in the first and second intrinsic semiconductor layers (X.sub.sj, X.sub.dj d), resulting in an MOS transistor.

Semiconductor device

A semiconductor memory device in which a plurality of unit memory cells are formed on a semiconductor substrate; each memory cell comprises a main electrode region provided with either of the source and drain sections of an MOS transistor, a gate region and an MOS capacitor region, the main electrode region, gate region and capacitor region being arranged in the order mentioned; a recess is formed in a semiconductor region including the gate region and part of the MOS capacitor region; the gate region is formed in one selected portion of the recess-defining wall body; and part of the capacitor electrode of the capacitor region extends over another selected portion of the recess-defining wall body.

Growing community of inventors

Kawasaki, Japan

Kenji Natori