Anritsu Electric Co., Ltd.

Kenji Nakatsugawa

Hiroshi Itaya

A phase detector is disclosed in which means are provided for sensing when two AC signals being subjected to phase difference measurement become close in phase, within a predetermined range, and for inverting one of these signals in phase when such a close phase relationship is sensed. The phase difference between the phase inverted signal and the other signal is then measured, and compensation is applied to the measured results such as to compensate for the effects of the phase inversion operation. Insensitivity and 'hunting' effects which occur with prior art phase detectors in the region of zero phase difference are thereby eliminated, and an output signal can be obtained which varies in a smooth and continuous manner with variations in the phase difference between the two signals under measurement, over a 360.degree. range.

Phase difference detector with phase inversion of one input signal when

In a multiprocessory system comprising a plurality of CPUs interconnected by a common bus, means are provided whereby the CPUs are periodically and cyclically enabled to access the bus. Data transfer from one CPU to another is performed by first storing the data into a main memory connected to the bus, then transferring the data from main memory to the destination CPU when the latter is enabled to utilize the bus and is in a condition to accept the data. Means can also be provided whereby, when data must be immediately transferred from one CPU to another, the sending CPU stores the data in main memory, generates signals whereby the destination CPU is given use of the bus, and generates an interrupt which causes transfer of the stored data into the destination CPU.

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Tokyo, Japan

Kenji Nakatsugawa