Fujitsu Corporation

Fujitsu Semiconductor Limited

Kenji Mukaida

Shoichi Masui

Masahiko Takenaka

Naoya Torii

Kouichi Itoh

Wataru Yokozeki

Michiya Oura

Tsuzumi Ninomiya

The computing device calculates an equivalence H&#x2261;2(mod n) relating to a divisor n of 2(step A), computes an equivalence H&#x2261;2(mod n) of 2(mod n) from Hby an REDC operation (step B), and performs a correction operation by H=REDC (H, G)for g=2when 2&#x3e;m&#xd7;k (step C).

Computation method, computing device and computer program

A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. The registers serve as buffer storage of multiple-word data to be supplied to individual input ports of the MAC operator. The amount of data supplied to the MAC operator in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle will be equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. This feature enables the use of a bandwidth-limited single-port memory, without causing adverse effect on the efficiency of MAC operator usage.

Multiple-word multiplication-accumulation circuit and montgomery modular multiplication-accumulation circuit

An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND, the parameter ND satisfying R&#xd7;R&#x2212;N&#xd7;ND=1 for an integer N and a radix R that is coprime to and greater than N, with a large number of effective lower bits. The device comprises an ND generator, a multiplication-accumulation (MAC) operator, and a sum data store. The ND generator produces effective lower bits of ND at a rate of k bits per clock cycle, with reference to lower k bits of a variable S, as well as to lower k bits of an odd positive integer N. The MAC operator multiplies the produced k-bit ND value by N and adds the resulting product to S. The sum data store stores the variable S, which is updated with the output of the MAC operator, with its bits shifted right by k bits, for use by the ND generator in the subsequent clock cycle.

Encryption/decryption system for calculating effective lower bits of a parameter for Montgomery modular multiplication

A programmable logic device with ferroelectric configuration memories storing multiple configuration data sets. The device has programmable logic blocks, interconnections, and I/O blocks to provide desired logic functions. Those building blocks can be dynamically reconfigured by changing the selection of configuration data stored in the device's integral configuration memories. The configuration memories are divided into groups, so that they can be loaded concurrently with multiple configuration data streams. To protect the content of configuration memories from unauthorized access, the device employs an authentication mechanism that uses security IDs stored in the configuration memories. The device has a memory controller to provide an appropriate power supply sequence for ferroelectric memory cells to ensure the reliable data retention when the device is powered up or shut down.

Growing community of inventors

Kawasaki, Japan

Kenji Mukaida