Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Kenji Misumi

Yutaka Terada

Yasuhiro Agata

Atsushi Fujiwara

Masanori Matsuura

Toshio Nishimoto

Makoto Kojima

Masanori Shirahama

Mitsuaki Hayashi

Wataru Abe

Masakazu Kurata

Hiroyasu Nagai

Masahiro Toki

Hideto Kotani

A circuit on an end column of a divided memory array is formed by a block selection transistor having the same shape as that of a memory cell transistor. As the pattern of the connecting section between the main bit line and the sub-bit line is made in the same shape as that of the memory cell, it is possible to realize a pattern uniformity and to eliminate the need for using memory array dummy patterns.

Semiconductor memory device with a selection transistor having same shape and size as a memory cell transistor

An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

Electronic equipment system and semiconductor integrated circuit controller

A memory controller outputs an additional writing instruction to one of a plurality of non-volatile memories arbitrarily selected via a writing instruction output unit when a signal which rejects a writing operation is not outputted from writing controllers of the plurality of non-volatile memories for a certain period of time, and outputs a temporary writing instruction to another non-volatile memory at least once via the writing instruction output unit by the time when the additional writing operation is completed in the arbitrary non-volatile memory.

Non-volatile memory control device

In a nonvolatile memory cell having a trap layer, programming or erasing is made in a sequence of first charge injection with a given wait time being secured and second charge injection executed after the first charge injection. Surrounding charge that deteriorates the data retention characteristic is reduced by use of initial variation occurring immediately after programming (charge loss phenomenon due to binding of injected charge with the surrounding charge in an extremely short time), and then the charge loss due to the initial variation is compensated, to thereby improve the data retention characteristic.

Nonvolatile semiconductor memory device and programming or erasing method therefor

Even when the number of rewrite operations varies among erase unit areas, the number of rewrite operations is improved for all of the erase unit areas. A flash EEPROMcomprises a trimming value storing areaof storing a trimming value corresponding to each erase unit areaincluded in a memory cell array. When an erase operation and a write operation are performed with respect to a certain erase unit area, a regulator circuitconverts a voltage boosted by a booster circuitto a level corresponding to the trimming value for the erase unit area. When a read determination circuitdetects an abnormality as the number of rewrite operations is increased, the trimming value is updated to a value which causes the regulator circuitto increase the output voltage.

Non-volatile memory device with threshold voltage control function

A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

Growing community of inventors

Kyoto, Japan

Kenji Misumi