Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Kenji Matsuo

Eiji Masuda

Kazuhiko Kasai

Yasoji Suzuki

Yasukazu Noine

Shinji Fujii

Ikuo Tsuchiya

Akira Yamaguchi

Itsuo Sasaki

Yasuhiko Fujita

Masahiro Kimura

Hiroaki Suzuki

Tadahiro Kuroda

Fuminari Tanaka

Hiroyuki Motegi

Shouji Abou

Hideaki Uchida

Masayo Fukuda

Ayako Hirata

Toshiyuki Fukunaga

Mitsuyuki Kunieda

Yoshihiro Kato

Akira Nagae

Kazuaki Umetsu

Minoru Takata

Tadashi Nonaka

A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.

Differential current source circuit in DAC of current driving type

In a sense amplifier circuit, an output potential is set in a data output state when an operation of the sense amplifier is a worst pass before the start of read access. In a memory read mode, when data corresponding to the worst-pass operation of the sense amplifier circuit is read out, the circuit is previously set in a corresponding data output state. A time delay (gate delay) by a gate does not occur. In contrast, when data corresponding to the best-pass operation of the sense amplifier circuit is read out, the gate delay occurs by this operation. The gate delay, however, is shorter than that of the worst pass. As a result, only the best pass is present as the operation mode of the sense amplifier circuit. Therefore, a high operation speed is achieved, so that a high read speed of the entire memory is achieved.

Sense amplifier circuit

The gate of a first P-channel transistor of a first comparator is supplied with an input signal, and the gate of a second P-channel transistor of the first comparator is supplied with a reference voltage. An output terminal of the first comparator is connected to an output circuit and the gates of first and second P-channel transistors of a second comparator are supplied with the reference voltage. The second comparator outputs a voltage equal to a stand-by time output voltage of the first comparator and the output voltage from the second comparator is supplied to the non-inversion input terminal of a third comparator which is connected to a voltage generating circuit. The voltage generating circuit has substantially the same dimension ratio as the output circuit and generates a voltage equal to the threshold voltage of the output circuit. A third comparator controls the first P-channel transistors of the first and second comparators in accordance with a difference voltage between the output voltage of the second comparator and the output voltage of the voltage generating circuit to thereby automatically set a stand-by time output voltage of the first comparator at a value close to the threshold of the output circuit.

Semiconductor integrated circuit capable of compensating errors in

This invention discloses a switching constant current source circuit including a first current path for supplying a constant current, a first MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a second current path, and a gate of which is applied with a digital signal corresponding to a logical amplitude, a second MOS transistor, one end of a current path of which is connected to the first current path, the other end of the current path of which is connected to a third current path, and which performs a switching operation complementary with the first MOS transistor, and level conversion means for fetching a change in voltage in the first current path caused by a change in current flowing through the first current path according to an operation of the first MOS transistor in response to the digital signal, and alternately applying a first level for disabling the second MOS transistor, which operates complementarily with the first MOS transistor, and a second level for enabling the second MOS transistor to output a predetermined current.

Switching constant current source circuit

A MOS transistor includes a gate electrode layer formed on an insulation layer which is formed on an element formation region defined by a field insulation layer formed on a P-type semiconductor substrate. The gate electrode layer has first and second openings formed therein. Further, N-type impurity diffusion regions acting as the drain and source of the MOS transistor are formed in those portions of the surface area of the semiconductor substrate which lie under the first and second openings.

MOS transistor and differential amplifier circuit with low offset

A low-noise output buffer circuit of this invention comprises a P-channel MOSFET having a source connected to a power source potential, for outputting the power source potential according to a first input signal, an N-channel MOSFET having a source connected to a ground potential, for outputting the ground potential according to a second input signal, a bipolar transistor having a collector connected to the power source potential, an emitter connected to an output terminal and a base connected to the drain of the P-channel MOSFET, and a diode having a cathode connected to the drain of the N-channel MOSFET and an anode connected to the base of the NPN bipolar transistor.

Low-noise output buffer circuit

This invention is a D/A converter including a preset current source, first and second differential switches for selectively deriving an output current of the preset current source in response to complementary signals supplied to control electrodes thereof, and an imaginary short circuit for connecting output portions of current paths of the switches to each other. Variation in the voltage at the time of switching operation of the differential switch can be suppressed by use of the imaginary short circuit with the above construction, thus making it possible to enhance the operation speed.

Differential current source type D/A converter

A semiconductor device comprises a first pad region applied with a first potential, a first line led from the first pad region and connected to a first circuit, a second pad region integrated with the first pad region and applied also with the first potential, and a second line led from the second pad region connected to a second circuit and overlapped with the first line.

Semiconductor device having multi-layered wiring structure

A delay circuit delays an input signal having a predetermined frequency by a time corresponding to a control signal. A delay amount detector detects a signal delay amount of the delay circuit. A charge pump circuit generates a DC voltage corresponding to a pulse width ratio between the input signal and a detection signal of the delay amount detector. This DC voltage is fed back to the delay circuit as a control signal.

Signal delay circuit using charge pump circuit

A voltage controlled oscillator comprises a phase locked loop section and a voltage controlled oscillator section. The phase locked loop section is coupled with an input signal at a reference frequency and a reference potential, and performs a signal feedback control so as to obtain a constant delay time of a first variable delay circuit contained in the phase locked loop section. The voltage controlled oscillator section controls a delay time of a second variable delay circuit in a ring oscillator by a control input voltage and an output voltage of a low-pass filter contained in the phase locked loop section, and produces a signal oscillating at a frequency as determined by the delay time. In the voltage controlled oscillator thus arranged, the output frequency is determined by controlling a delay time of the second variable delay circuit in the voltage controlled oscillator section. Since the delay time is accurately controlled by the phase locked loop section, the obtained output frequency is stable against the variance of the process parameters. Since the delay time is varied by the reference frequency of the input signal, the output frequency may be set at a desired frequency, and hence a frequency band of the oscillation frequencies may also be set appropriately.

Voltage controlled oscillator

A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V.sub.DD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source V.sub.SS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.

MOS pull-up or pull-down logic circuit having equalized discharge time

A voltage comparison circuit having an amplification circuit which includes an inverting amplifier and a switching MOS transistor for setting an operation point of the inverting amplifier connected between input and output terminals of the inverting amplifier. The amplification circuit further includes at least one low-pass filter connected in a closed loop including the inverting amplifier and the switching MOS transistor.

Voltage comparison circuit with ripple component elimination

A semiconductor switching circuit includes a MOS inverter and a switching MOS transistor for executing a switching operation in response to the output signal from the MOS inverter. The semiconductor switching circuit further includes a low-pass filter coupled between the MOS inverter and the gate of the switching MOS transistor.

Semiconductor sample and hold switching circuit

A parallel analog-to-digital converter circuit comprises a plurality of level comparator circuits and a plurality of detectors. The level comparator circuits compare the level of one analog input signal with a plurality of reference levels. Any two or more level comparator circuits which receive consecutive reference levels from one set. Each of the detectors determines whether or not the output signals from the level comparator circuits of one set are in a specified state. According to the number of sets of level comparator circuits whose output signals are detected to be in the specified state, it is determined whether or not the analog-to-digital converter circuit functions correctly. the upper limit of the speed of analog-to-digital conversion can be determined according to this number of sets.

Parallel analog-to-digital converter circuit

An analog switch circuit which is provided with a transmission gate consisting of a first n channel MOS transistor and a first p channel MOS transistor, which transistors are connected in parallel, wherein the output terminal of said transmission gate is connected to a second n channel MOS transistor and a second p channel MOS transistor, which transistors are supplied with an output voltage Vout from the transmission gate, and wherein mirror capacitances C.sub.mP12, C.sub.mP13, C.sub.mN12, C.sub.mN13 are provided at the output terminal of the transmission gate to offset a difference between the mirror capacitance C.sub.mN11 of the first n channel MOS transistor and the mirror capacitance C.sub.mP11 of the first p channel MOS transistor.

Growing community of inventors

Yokohama, Japan

Kenji Matsuo